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An analytical subthreshold surface potential in an short-channel MOS transistor, incorporating the fringing fields at the two ends of the device, is proposed. For short channel devices, the effect of the source and drain edge electric fields around the source and drain junctions on the surface potential is very important. In this model we included this edge electric field. This gives a more accurate...
The adder circuit is used as a main component in the multiplier circuits. The Baugh-Wooley, Braun and CSA multipliers are designed by using our proposed adder cell. The proposed adder circuit is designed by using Shannon theorem. The multiplier circuits are schematised by using DSCH2 VLSI CAD tool and their layouts are generated by using Microwind 3 VLSI CAD tool. The proposed adder based multiplier...
In this paper a kind of ESD protection design scheme named GDNMOS (gate driven NMOS) is investigated. GDNMOS is used more and more wildly for its excellent performance in submicron CMOS VLSI ESD protection. NMOS, inverter and the RC couple cell are the makeup in this scheme. ESD device simulation in order to evaluate the robustness of the ESD protection device is performed firstly. Device simulation...
This paper proposes a ZSCTS methodology aiding in zero skew clock tree synthesis suitable to the mainstream industry clock tree synthesis (CTS) design flow. At the gate level, the original clock net is broken up into smaller partitions, and the clock buffers are inserted as pseudo clock sources to drive each portion. The automatic place and route (APR) tool may synthesize each clock subtree with better...
Ternary codes have been widely used in radar and communication areas, but the synthesis of ternary codes with good discrimination factor is a nonlinear multivariable optimization problem, which is usually difficult to tackle. To get the solution of above problem many global optimization algorithms like genetic algorithm, simulated annealing, and tunneling algorithm were reported in the literature...
This paper presents a model of the output transition time suitable for nanometer CMOS gates. The proposed modeling approach separately analyzes the output transition time under fast and slow inputs, according to the basic concept of the model in. The model so developed is very simple and preserves a clear physical meaning. These highly desirable characteristics allow for an efficient implementation...
With a limited number of pre-constructed gates available, current standard cell libraries are not well equipped to take full advantage of advances in deep submicron technology by implementing functions as complex gates. As reported, in a technology process capable of supporting five serial MOS devices, 425,803 unique complex gates may be created - clearly much higher than what is currently available...
Recently, to realize large real-time systems, demands for fast computation on large VLSI have continued to increase. An optically reconfigurable gate array has been developed to realize large virtual gates. As part of that research effort, the world's largest 11,424 gate-count dynamic optically reconfigurable gate array VLSI chip, which is based on a concept using junction capacitance of photodiodes...
Recently, optically reconfigurable gate arrays (ORGAs) consisting of a gate array VLSI, a holographic memory, and a laser array have been developed to achieve huge virtual gate counts that is much larger than those of currently available VLSIs. Using ORGA architecture, greater than 1 tera gate count VLSIs are possible by exploiting the storage capacity of a holographic memory. Conventional ORGAs have...
This paper reviews silicon implementations of threshold logic gates, covering several decades. It details numerous VLSI implementations including: capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS, output-wired-inverters, and a plethora of solutions evolved from them), as well as many differential solutions. Nanoelectronic implementations (e...
For arithmetic circuits, it is important to maximize the speed and to minimize the power consumption, which may be accomplished by minimizing the product of the delay and the power consumption. The authors discuss the speed and the number of logic transitions (a measure of power dissipation for static CMOS circuits) of several different parallel multipliers. The circuits are constructed with inverters...
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