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The paper deals with dynamic supply current (iddt) test method, where several parameters of the iddt waveform have been monitored. Simulations were performed on two 64-bit SRAM circuits, in which resistive open defects were investigated. The technologies used were 0.35 μm and 90 nm CMOS. The efficiency of iddt test in covering open defects for both technologies was evaluated.
A latch-type sense amplifier (SA) utilizing adaptive resistance technique is proposed. With adaptively adjusted resistance in a latch path, the proposed SA can compensate for an erroneous voltage drop in bit-lines induced by bit-cell leakage current. The simulation shows that the sense amplifier margin (SM) is improved in the presence of mismatches. The SA test chip is fabricated in a 0.18-μm CMOS...
Today's main stream NVM technologies require operational conditions that are incompatible with modern low voltage logic CMOS designs. This characteristic results in complex integration issues as well as costly process and array concept especially for embedded NVM use models. Conductive bridging memory cell (CBRAM) technology is an attractive emerging memory technology that offers simple integration...
The contact resistance of CMOS device increases sharply withtechnology scaling, especially in SRAM cells with minimum size and/or sub-groundrule devices. Meanwhile, VT drifts caused by Negative-Bias Temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of nanoscale SRAM with high-kappa metal-gate devices over the lifetime of usage...
Emerging concepts of non-volatile memories are more and more investigated to replace conventional charge storage-based devices like EEPROM or Flash. One of these promising memory concepts is called Resistive Switching Memory (ReRAM). Such memory is based on a switching mechanism controlled in current and/or voltage, between two distinct resistive states depending upon the material nature integrated...
The multi-level operation of WOx based RRAM has been investigated. Improvement of our WOx process has produced an extended linear R-V region for our devices. By adding an electrical forming process and a program-verify algorithm we have demonstrated stable 2-bit/cell operation, with potential for 3-bit/cell. The reliability of the MLC operation has been examined and very stable high temperature retention,...
This paper analyzes the crystallization statistics and optimizes the performance of complex doped GST on 256 kb memory arrays in 180 nm CMOS technology. A novel method of deriving an optimized SET strategy from the RESET current distribution is developed. This significantly improves performance and results in 200 ns SET time. A large Rreset/Rset ratio can be maintained even after 8E6 cycles.
A nonvolatile static random access memory (NVSRAM) cell with two back-up CuxO memory devices is proposed in this paper. The manufacturing process is compatible with the standard CMOS process. By adopting a dynamic supply voltage scheme, the proposed cell can work correctly in four different operation modes. Compared with the standard SRAM cell, the proposed cell offers non-volatile storage which allows...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
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