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This paper addresses the design of the mapping tool used for the FPGA application implementation in our SRAM-based FPGAs fabricated in a 0.5 micron SOI-CMOS process. Comparing with the existing mapping tools from academia, we propose several techniques of packing and clustering to improve the technology mapping. The proposed algorithms provide a closer matching of the user logic netlist with the underlining...
With the scaling of submicron device dimensions, the current density and the temperature of interconnects have increased many folds leading to component failure due to electromigration. This paper analyzes the effect of electromigration failures in the interconnect of SRAM-based Field Programmable Gate Arrays (FPGAs). The Mean Time to Failure (MTF) of interconnects is calculated for different benchmark...
Field programmable gate arrays (FPGAs) is becoming one of the most widely used electronics devices. Because of its unique architecture, power estimation is a complicated task for FPGAs. This paper presents a novel power estimation framework for SRAM-based FPGAs. Considering both dynamic power and static power, a gate-level power model for configuration logic blocks (CLBs) and a transistor-level power...
As technology scales and the geometries of the transistors shrink, leakage current and subsequently total power consumption increase considerably. Many of the benefits brought forth by the smaller transistors will be lost if the high power consumption problem cannot be solved. The leakage power consumption problem is especially relevant to an FPGA because of the amount of unused interconnect and logic...
Static-random-access-memory(SRAM)-based field programmable gate arrays (FPGAs) consists of 50% ~70% routing resources. A simple programmable interconnect point (PIP) is a switch controlled by SRAM configuration cell connecting two wires. A novel traverse algorithm targeted for the detection of PIP open faults is proposed. Experimental results run on the Fudan design system (FDS) platform show that...
This paper presents a novel build-in-self-test (BIST) manufacture-oriented interconnect test strategy of SRAM-based field programmable gate arrays (FPGA). Programmable switches (PSs) and line segments are tested separately, which is different from previous methods. An improved depth-first-search (DFS) algorithm is developed for automatically deriving minimal or near minimal test configuration patterns...
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
Reconfigurable logic devices such as SRAM-based field programmable gate arrays (FPGAs) are nowadays increasingly popular thanks to their capability of implementing complex circuits with very short development time and for their high versatility in implementing different kind of applications, ranging from signal processing to the networking. The usage of reconfigurable devices in safety critical fields,...
In this paper we present an analytical analysis of the fault masking capabilities of triple modular redundancy (TMR) hardening technique in the presence of multiple cell upsets (MCUs) in the configuration memory of SRAM-based FPGAs. The analytical method we developed allow an accurate study of the MCUs sensitiveness characterizing the orientation and the effects provoking multiple domain crossing...
This paper proposes a delay model for SRAM-Based FPGA Interconnections. First, an equivalent resistance delay model is presented based on 50% timing delay for step input. The equivalent capacitance delay model is thereafter proposed for the ramp input The corresponding effective capacitance delay calculation method is also given. The experimental results show the efficiency and accuracy of the proposed...
Integrating an embedded FPGA into SoC allows post-fabrication changes. Thanks to their unlimited reconfigurability, eFPGAs are able to implement specific functions, thus improves the systems performance. In this paper the authors present an SRAM-based eFPGA architecture. The authors explore the hardware aspects of the eFPGA including internal structure and external coupling with a VCI interconnect...
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