The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Digital computations and calculations is involved in every embedded and processing device, these devices has arithmetic logic unit or a special block to perform a desired operation, Addition can be one such operation, adders are most important and fundamental block used for Addition, Subtraction, Multiplication, Division, Address generation and so on, design and selection of adders for a embedded...
This paper proposes an effective model for evaluating vertical signal propagation delay in through silicon via (TSV) based three-dimensional integrated circuits (3-D ICs). The capacitance model for on-chip interconnects is also proposed. All parasitic parameter values for an entire structure can be calculated by the closed-form equations. The delay model is constructed with the first- or second-order...
This paper addresses the trajectory tracking problem of intake burned gas rate for Spark Ignited engines. We propose a simple linear time-varying input delay model of this dynamics, where the delay is represented by an implicit integral equation involving the past values of the input. We extend some recent results from the literature to design a novel predictor-based controller and compare the merits...
In the nanometer era, the mismatch between the pre-silicon model and the post-silicon timing behavior is becoming severer. Therefore, it is necessary to validate timing with post-silicon data. We propose a method that estimates all the segment delays in the observed paths of a design from post-silicon path delay measurements. Our method is based on equality-constrained least squares methods, which...
This paper studies the TSV-to-TSV coupling issues in 3D ICs and introduces a methodology for performing signal integrity (SI) analysis considering TSV-to-TSV coupling for 3D ICs. 3D SI analysis results show that TSV coupling has big impact on the SI in 3D ICs. A TSV-KOZ sizing methodology and a force-directed placement-refinement approach are proposed to alleviate the 3D SI problem. Experimental results...
Electrothermal characterization of single-walled carbon nanotube (SWCNT) field effect transistors (CNTFETs) is performed in this paper. By solving one-dimensional heat conduction equation in the channel self-consistently, self-heating effects on the I-V characteristics, signal delay and cutoff frequency of the CNTFET are studied. Simulated results indicate that the performance degradation of the CNTFET,...
Time-delay systems described by couple differential-functional equations include as special cases many types of time delay systems and coupled differential-difference systems with time-delays. This article discusses the discretized Lyapunov-Krasovskii functional (LKF) approach for the stability problem of coupled differential-difference equations with multiple discrete and distributed delays. Through...
Traditional diagnosis of defects is based on an assumed fault model. A failing chip is diagnosed to find the subset of faults that can best explain the failure. This paper illustrates a link between this traditional perspective of diagnosis and a new perspective where diagnosis is seen as a form of data learning. We explain that both defect diagnosis and data learning are solving so-called ill-posed...
There are many communication imperfections in networked control systems (NCSs) such as varying sampling/transmission intervals, varying delays, possible packet loss, communication constraints and quantization effects. Most of the available literature on NCSs focuses on only some of these phenomena, while ignoring the others, although recently some papers appeared that consider at least three of these...
Considering the characteristics of the propagation of worm, we can analyze it by epidemic model. In this paper, considering that to re-assembly system and the use of anti-virus software will take a period of time, so we introduce a time-delay to describe this period of time. On this basis, we build a SIDRQ model for Internet worm virus propagation depended on the two-factor model. By using the theory...
Multipoint-to-multipoint message broadcast is a demanding application scenario in ad-hoc networks. Adaptive management of wireless resources is necessary to support such applications in a safety critical context. In this work we study adaptation of transmission rate and power to varying densities of ad-hoc nodes. Our approach is to construct a cross-layer model building on existing models for physical...
This article discusses the Lyapunov-Krasovskii functional method for the stability problem of coupled differential-functional equations with distributed delays and one discrete delay. However, systems with distributed delays and multiple commensurate discrete delays can be easily transformed to the standard form treated in this article. This standard form represents a very general class of time-delay...
Due to the increased random variations in nanometer silicon process technology as well as voltage and temperature variations, it is very hard to guarantee performance characteristics with traditional corner-based timing analysis method. The variations, together with the issues like crosstalk and jitter, make it difficult to get a good silicon correlation with simulation and to meet target performance...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
In this work, we have performed a thorough study of the mobility in `Si / s-Ge / Si' QW heterostructure pMOSFETs. We have been able to accurately fit experimental data obtained from ultra-thin strained-Ge QW FETs by theoretical calculations, in which the hole sub-band structure is calculated by 6??6 k.p Poisson-Schrodinger equation, and all the important scattering mechanisms (acoustic phonon, optical...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
We present a generic method for analyzing the effect of process variability in nanoscale circuits. The proposed framework uses kernel and a generic tail probability estimator to eliminate the need for a-priori density choice for the nature of circuit variation. This allows capturing the true nature of the circuit variation from a few random samples of its observed responses. The data-driven, non-parametric,...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
Real time applications are characterized by their delay bounds. To satisfy the Quality of Service (QoS) requirements of such flows over wireless communications, we enhance the 802.11 protocol to support the Deadline Mono- tonic (DM) scheduling policy. Then, we propose to evaluate the performance of DM in terms of saturation throughput and average medium access delay called average service time. Therefore,...
As technology is aggressively scaled, nano-regime VLSI designs are becoming increasingly susceptible to process variations. Unlike pre-silicon optimization, post-silicon techniques can tune the individual die to better meet the power-delay constraints. This paper proposes a variation-aware methodology for the simultaneous gate sizing and clustering for post-silicon tuning with adaptive body biasing...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.