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A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is proposed to improve the power efficiency. An input offset storage technique of dynamic comparator is proposed to increase the conversion linearity. A reference voltage buffer with the charge compensation is proposed to save power and reduce the...
A low-power multi-standard transceiver in CMOS 28 nm is presented. The transceiver can be configured to cover the range from 5 Gbps to 28.2 Gbps. Both transmitter and receiver use a supply of 0.92 V. Transmitter uses a 3-tap Finite Impulse Response (FIR) filter and receiver uses a 3-tap analog FIR and 2-tap unrolled Decision Feedback Equalizer (DFE). The entire transceiver uses single level 0.92 V...
The emerging broadband ISDN will satisfy the present and future needs for a wide range of bit rales and holding times. A broadband ISDN subscriber access prototype[1][2] PI being explored at Bell Communications Research includes highspeed circuit switching, time division multiplexing, packet multiplexing, and packet processing. In order to properly identify data streams in the network, and to allow...
Many important fields for the application of semiconductor ICs (e.g. digital communication networks, factory automation, office automation) are governed by processing digital data streams. Often these data streams are split into parts, which are processed separately. Afterwards usually synchronization is necessary, because different latencies occur in each processing unit. A delay circuit, which is...
A 1.2 V, 10 b, 40 MS/s pipelined ADC fabricated in 0.13µm one-poly eight-metal (1P8M) standard CMOS process with MIM capacitors is presented. This ADC used a novel low-variation on-resistance CMOS sampling switch to improve the nonlinear effect and a two-stage recycling folded-cascode (RFC) amplifier with hybrid frequency compensation for power saving and low voltage supply requirements. By implementing...
This paper presents an implementation of a binary pulse-position modulator (2-PPM) for impulse-radio ultra-wideband (IR-UWB) systems, capable of producing an appropriate signal to drive the final output stage of an ultra narrow pulse generator. Compared to the usual circuits based on voltage-controlled delay lines, this novel scheme uses digital signal processing of the clock and data signals with...
A wide-locking range divide-by-4 static frequency divider for the mm-wave wireless applications is proposed. The capacitive-bridged inductive shunt peaking technique is investigated for widening the locking range and a compact layout area. The divider is realized in 65nm LP CMOS with a small area of 100μm × 160μm occupied. Measurement results show the present divider achieves an operation range percentage...
The possibility of recovering sensible information through the observation of dynamic power consumption of a cryptographic device is a critical issue in security applications. As it has been widely demonstrated in the literature, it is possible to reveal the secret keys of a cryptographic device exploiting the information leaked by the implementation through the power side channel. An on-chip, analog,...
In this paper we present a 10-phases programmable clock generator for the application in control of Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC), realized in the CMOS 130 nm technology. The circuit provides 10 clock signals on separate terminals (sections). The programmable feature means that we can program the number of clock phases which are cyclically repeated. The...
A comparator-based circuit that uses switched-capacitor charging replaces the op amp in the multiplying digital-to-analog converter (MDAC) of a low-voltage algorithmic ADC. MDAC output swing beyond Vdd allows greater than rail-to-rail ADC input range. At a supply voltage of 0.55 V, the ADC achieves 8.4 bit ENOB and 1.4 Vpp differential input range. It occupies 0.65 mm2 in 0.25-μm CMOS and dissipates...
This paper presents a temperature and supply voltage variation-tolerant CMOS relaxation oscillator which is suitable for ultra-low power systems. A low-power low-cost half-period pre-charge compensation scheme is proposed to eliminate influences of the delay of the comparator and the RS latch on the frequency stability of the relaxation oscillator. In a clock period consisting of four working stages...
This paper presents a novel pipeline configuration for wireless applications. Redundancy and multi sampling of the input techniques are used for overcoming the main limitations of pipeline ADCs. A special pre-amplifier with built-in thresholds generation is also discussed. The circuit, designed and simulated in a 65-nm CMOS technology, achieves 2.66 GS/s and 8-bit resolution. The supply voltage is...
A high-speed low-power 1:16 demultiplexer with a novel symmetrical-edge-delay sense amplifier is presented in this paper. The traditional Sense-Amplifier-Based Flip-Flop (SAFF) has asymmetric rising and falling edges with the fact that the falling edge lags the rising edge the time of a gate delay, which has become a bottleneck of speed. In order to overcome the problem of nonsymmetry of output data...
A scalable 7.0-Gb/s/lane, 6-lane serial link transceiver for chip-to-chip NRZ data communication is described. Its serializing transmitter uses a new circuit topology, with data-controlled pulse generation followed by pulse-controlled serialization, and provides improved bandwidth and power efficiency with the elimination of on-chip NRZ signaling and retiming while preserving the bandwidth benefit...
In this paper, a hybird adaptive Coordinate Rotation Digital Computer (HA-CORDIC) has implemented in 65nm Silicon On Thin Buried oxide (SOTB) CMOS technology. In the HA-CORDIC implementation, the adaptive algorithm is utilized for reducing the iteration of CORDIC algorithm. In comparison with other floating-point CORDIC designs, the latency of our proposed scheme is lower. It spends only 12, 20, and...
In this Paper, we propose a new method for safe electrical neural stimulation. Current mode digital-to-analog converters are used to generate the cathodic and the anodic stimulation phases. A sample-and-hold and a window comparator circuit are used to compare the voltage of the electrode and the tissue with a target value within a safe voltage range of −50 mV to +50 mV. When the electrode voltage...
An explosive growth in the number of IT devices connected to a central system requires massive growth in aggregate bandwidth of wireline communications. As a result, a multi channel architecture is necessary in the high-speed I/O link to meet the ever increasing bandwidth requirement. Forwarded clock (FC) architecture offers the most efficient solution for the multi-channel I/O owing to the shared...
This paper presents a 96.6-dB-peak-SNDR and 50-kHz-bandwidth switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW. This performance is achieved by the introduction of Class-AB single-stage switched variable-mirror amplifiers (VMAs) combined with an optimized architecture and a 5-phase switched-capacitor scheme. The resulting 1.8-mm2 delta-sigma modulator is integrated...
The performance of priority encoder circuits is usually limited by the delay associated with the propagation of the priority token, however, proper design in the architectural level can reduce the delay stages to the order of O(log n). Furthermore, power dissipation and area pose an increasingly important concern in modern circuit design, thus the development of suitable techniques is essential. This...
Multiport CMOS cell with the soft-error immunity based on DICE which is divided into two spaced groups of transistors each of them consisting of four transistors. The larger the distance between these two CMOS transistor groups, a multiport SRAM is more hardened to single event upsets. The result of a single nuclear particle strike only on the one transistor group of a DICE trigger is a single-event...
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