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This paper proposes an approach for testing of safety critical systems. It is based on a behavioral and a fault model. The two models are analyzed for compatibility and necessary changes are identified to make them compatible. Then transformation rules are used to transform the fault model into the same model type as the behavioral model. Integration rules define how to combine them. This approach...
This paper proposes an approach for testing of safety critical systems. It is based on a behavioral and a fault model. The two models are analyzed for compatibility and necessary changes are identified to make them compatible. Then transformation rules are used to transform the fault model into the same model type as the behavioral model. Integration rules define how to combine them. This approach...
A software is associated with certain modes of failure. Occurrence of such failures may be hazardous for the regular functioning of the software. Majority of these failures occur because of the unforeseen faults that manifest themselves during the execution of the software. The contemporary trends in the software industry indicate dedicated efforts to minimize these unforeseen faults, thereby minimizing...
In the practice of process-centric systems implementations, business process modeling is becoming more crucial. This paper introduces an approach to automatically generate test suites for the process paths to check the consistency, which is very important, between the business process model and the implementation of Enterprise System. The paper also presents a supporting tool to apply this approach...
Post-silicon testing and validation - whether to screen out defective parts, confirm proper operation in the target application, or test robustness in the presence of transient issues induced by environmental factors - is especially crucial for safety-critical devices. These activities sometimes leverage information gathered prior to fabrication through the injection and testing of stuck-at and transient...
Testing NAND flash memories is a very complex issue due to the rapid scaling down of the technology and the related floating gate reliability issues: as a consequence a complete and technology independent test is needed. Several faults and disturbances were identified both for NOR and NAND flash memories: however they has never been considered together as a whole. In this work we analyze all the possible...
Critical path selection plays an important role in testing of small delay defects (SDD). For some timing-balanced circuits, the numbers of candidate critical paths may be very large, and this will make Monte Carlo simulation based statistical timing analysis very inefficient. A fast path selection approach based on graph partition is proposed in this paper. First, a critical path graph (CPG) is generated...
Defective part levels of zero are almost impossible to achieve in an era of complex defects, process variations, and limited testing resources. It is important to ensure that any defects missed during test will impact the end user as little as possible. However, optimizing test sets for superior detection of critical defects requires an understanding of relative fault criticality, and this determination...
This paper presents a novel approach to verify the correct implementation of Triple Modular Redundancy (TMR) for the memory elements of a given netlist using formal analysis. The purpose is detecting any issues that might incur during the use of automatic tools for TMR insertion, optimization, place and route, etc. Our analysis does not require a testbench and can perform full, exhaustive coverage...
Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the...
We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
One effective fault injection approach involves instrumenting the RTL in a controlled manner to incorporate fault injection, and evaluating the behaviour of the faulty RTL whilst running some benchmark programs. This approach relies on checking the effects of faults whilst the design is executing a specific binary image, and therefore the true impact of the fault is limited by the shadow of the program...
The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this...
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies and the trend is expected to get worse. Soft error rate (SER) measurement, expressed as number of failures encountered per billion hours of device operation, is time consuming and involves significant test cost. The cost stems from having to connect a device-under-test to a tester for...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm CMOS technologies. In the present work the soft-error rate (SER) of a 65-nm flip-flop has been investigated with the use of alpha-accelerated testing. Simulations have been applied to study the flip-flop SER sensitivity in detail. Furthermore, an easy-to-use approach is presented to make an accurate...
Transient faults have become increasingly observable in combinational logic. This is due to the weakening of some inherent protective mechanisms that logic traditionally holds against such flawed spurious events. One of the aforementioned mechanisms relates to the propagation of transient faults along sensitizable paths. Existing literature that relies on logic simulation under estimates the number...
As software systems are encompassing a wide range of fields and applications, software reliability becomes a crucial step. The need for safety analysis and test cases that have high probability to uncover plausible faults are necessities in proving software quality. System models that represent only the operational behavioral of a system are incomplete sources for deriving test cases and performing...
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently...
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