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Several field-effect transistor (FET)-based device technologies are emerging as powerful alternatives to the classical metal oxide semiconductor FET (<sc>mosfet</sc>) for computing applications. The focus of this paper is on the analysis of reliability of combinational logic circuits at the transistor level with the goal of application to these technologies. To this end, we present an...
Lowering the supply voltage below the threshold voltage of the transistors brings important benefits regarding the power consumption. However, the main issue of sub-threshold CMOS circuits is the abrupt reliability decrease. This paper proposes a simulated fault injection approach for reliability assessment of gate-level designs supplied at low voltages. The proposed method uses previously determined...
The reliability of digital circuits is greatly distorted as the VLSI design cycle enters into nanoscale arena. In the past, the inputs of digital circuits were considered deterministic but shifting of transistor technology into nanoscale dimensions has made their behaviour totally probabilistic. The reason is that logic level voltages suffer from a number of fluctuations due to the effect of signal...
Reliability analysis of combinational circuits has become imperative these days due to the extensive usage of nanotechnologies in their fabrication. Traditionally, reliability analysis is done using simulation or paper-and-pencil proof methods. But, these techniques do not ensure accurate results and thus may lead to disastrous consequences when dealing with safety critical applications. In this paper,...
Static statistical variability and time-dependent reliability are traditionally analyzed separately. This paper presents a new methodology which combines both types of variability within a single circuit analysis framework. A comprehensive Negative Bias Temperature Instability (NBTI) model was implemented. Effects of random discrete dopants, line edge roughness and poly-Silicon granularity were considered...
As CMOS technology is reaching the nanometer scale, transient and intermittent faults occurrence in logic circuits, which implies a reliability degradation, can no longer be neglected. This paper deals with reliability evaluation which is a critical parameter in circuit design. The proposed method is scalable, iterative and accelerates the reliability analysis.
Aggressive scaling of CMOS transistors in last four decades has resulted in circuits with progressively higher packing density, increased switching speed, and higher power density. However in future, CMOS technology nodes are predicted to suffer from greater intermediate to long-term reliability and circuit marginality problems. To address these problems researchers have proposed the usage of redundant...
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect...
In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR...
Reliability analysis of digital circuits is becoming an important feature in the design process of nanoscale systems. Understanding the relations between circuit structure and its reliability allows the designer to implement some tradeoffs that can improve the resulting design. This work presents a probabilistic model that computes the reliability of combinational logic circuits relating to single...
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