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In this work, we propose a fast tool to compute the variation (σ/μ) of delay for any logic path in a synthesized design for any given process corner. The proposed method does not require deep understanding of device physics, prior knowledge of the design, or extensive Monte Carlo simulation, and it provides good accuracy with less than 11% error. We also demonstrate the importance of using variation...
A new algorithm for neutral point voltage imbalance estimation in DC link of the three-level (3L) neutral point clamped (NPC) voltage source inverter (VSI) is proposed. Application of the proposed algorithm does not require any additional sensors. The unbalanced voltage calculation is based on the information derived from the inverter output measured currents and from the knowledge of the load model...
When large penetration of the distributed generators (DGs) such as photovoltaic (PV) systems is growing up in grid system, it is important to quickly prevent islanding caused by power system fault in order to ensure electrical safety. We propose a novel active method for islanding prevention by harmonic injection synchronized with exciting current harmonics of the pole transformer in order to avoid...
This paper describes a method to enhance the load frequency control in a power system with distributed generations (DG). In this paper, a power storage system is used with photovoltaic generation and wind power generation. The microgrid system at Aichi Institute of Technology in Japan is used as a simulation model. For each simulation, which was carried out by using a power transmission simulator,...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
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