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Network-on-chip (NoC) has been introduced as a promising on-chip communication architecture to support many IP (intellectual property) cores on a single chip. Application mapping of IP cores onto a NoC topology is considered as a NP-hard problem. The increasing number of IP cores makes NoC application mapping more challenging to obtain optimum core-to-topology mapping. This paper proposes a genetic...
This paper presents a method to extract global order of transactions from local partial orders in NoC tiles. The ordering method is based on our set of “happened-before” rules, assuming transactions do not have a timestamp. The assumption is based on the fact that implementation and usage of a global time as timestamp in such systems may not be practical or efficient. We have improved the extracted...
A Network-on-Chip (NoC) is a new paradigm in complex System-on-Chip (SoC) designs that provides efficient on-chip communication architecture. It offers scalable communication to SoC and allows decoupling of communication and computation. In NoC, design space exploration is critical due to trade-offs among latency, area, and power consumption. Hence, analytical modeling is an important step for early...
This paper proposes a new dimension order routing algorithm for Mesh-of-Tree based Network-on-Chip design. It simplifies the router design as well. It results in significant saving in the energy consumed by the network. For uniform traffic, the saving is as high as 63%. It offers the flexibility of designing routers of different sizes for mapping of applications.
Multiprocessor System on Chip (MPSoC) are increasingly considered as the post promising solution for complex embedded applications. The most significant MPSoC design challenge comes from interconnect infrastructure. Network-on-Chip (NoC) with multiple constraints to be satisfied is a promising solution for these challenges. It has been shown that infrastructure topology; routing and switching schemes...
The ever increasing density of integration makes the NoC a relevant communication design paradigm even for FPGAs. But NoC are always designed without considerations of applications and programming models, like busses and crossbars. Dealing with parallelism is still challenging. One way is to take into account the parallel programming model and application field in the design of the NoC, to reduce...
Flow control in Network on Chip (NoC) is critical because unbalanced transmission process and congestion in nodes can affect on-chip performance: communication latency, throughput and heat accumulation. To achieve the goal to balance on-chip communication load, we present a distributed routing scheme named RIPNoC (Router Information Piggybacking Routing Scheme for NoC). This routing scheme provides...
A new hierarchical genetic algorithm for low-power network on chip (NoC) design is proposed in this paper. As 2D-mesh is a widely used NoC topology, this paper studies the optimization of mapping IP (intellectual property) cores onto regular and irregular 2D-mesh network while minimizing communication power consumption. Experimental results show that significant energy savings can be achieved. For...
Bus and mesh based Networks-on-Chip (NoC) are two different architectures of on-chip communication. Each of them has different features and applications. In this paper, we combine these two architectures and construct a hybrid one. In the hybrid architecture, the IP cores with heavy communication affinity are placed in the same subsystem, and a large mesh NoC is partitioned into several subsystems...
3D IC technology drives Network-On-Chip (NoC) design on towards 3D trend and relevant multi-core system further development. However, most recent researches still focus on the fundamental 3D Mesh structure and have no convincible traffic pattern models in realistic applications. In this paper, we p resent a complete design framework of a Distributed Shared Memory homogenous multi-core system based...
Power characteristics of different Network on Chip (NoC) topologies are developed. Among different NoC topologies, the Butterfly Fat Tree (BFT) dissipates the minimum power. With the advance in technology, the relative power consumption of the interconnects and the associate repeaters of the BFT decreases as compared to the power consumption of the network switches. The power dissipation of interswitch...
Shrinking transistor sizes and recent trends toward many-core chips have heightened the need for an efficient on-chip communication network to integrate various cores. However, buses and point-to-point interconnection will not result in scalability, modularity, and explicit parallelism, as well as may suffer great performance bottleneck. While state-of-art packet-switched network increases the communication...
A 118.4 GB/s multi-casting network-on-chip (MC-NoC) is proposed as communication platform for a real-time object recognition processor. For application-specific NoC design, target traffic patterns are elaborately analyzed. Through topology exploration, we derive a hierarchical star and ring (HS-R) combined architecture for low latency and inter-processor communication. Multi-casting protocol and router...
In this paper, we propose a new 2.5D NoC architecture that uses a homogeneous network on one layer on top of a heterogeneous floorplanning layer. The purpose of this approach is to exploit the benefits of compact heterogeneous floorplans and regular mesh networks through an automated design space exploration procedure. A design methodology consisting of floorplanning and router assignment in a specifically...
In this paper we approach the performance aspects of MPSoC platforms, from the point of view of IP placement with the focus on network-on-chip (NoC). Proper IP placement is important for several time-dependent applications such as video and voice where traffic must be delivered on time in order to operate properly. Proper placement of IPs can lower the traffic congestion, improve overall execution...
A 118.4 GB/s multi-casting network-on-chip (MC-NoC) is developed as communication platform for a real-time object recognition processor. To support application-specific data transactions, the MC-NoC adopts the combination of hierarchical star and ring topology with the multi-casting capability. As a result, the proposed MC-NoC improves data transaction time and energy consumption by 20% and 23%, respectively,...
Network-on-chip mapping and the configuration of the communication parameters are critical process of the NoC design. They significantly influence the performance, area and power of the NoCs. We take the NoC mapping problem and the design of the communication parameters both into account. First, we formalize the problem of NoC mapping. Then we propose an analytical delay model based on wormhole switching...
This paper explores the possibility of building a flexible Low Density Parity Check (LDPC) decoder using a network on chip communication infrastructure. Even if this idea is not completely new, previously published works suffered from an excessive area occupation and their practical impact has been very limited. In the following we analyze two possible NOCs specifically designed for the LDPC case...
The design flow of network-on-chip (NoCs) include several key issues. Among other parameters, the decision of where cores have to be topologically mapped and also the routing algorithm represent two highly correlated design problems that must be carefully solved for any given application in order to optimize several different performance metrics. The strong correlation between the different parameters...
Topology selection is an important issue for the design of network on chip systems. At present, typical application-specific NoC systems often integrate a number of heterogeneous components which have varied functions, sizes and communication requirements. Instead of regular topology networks which are not suitable for this sort of NoC systems, irregular mesh network is proposed and applied in NoC...
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