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With the widespread use of solar energy, the grid-connected photovoltaic (PV) systems based on solid state transformer (SST) have considerable prospect. This paper presents the design and demonstration of a three-phase 800-V/10-kV 1-MW SST for grid-connected PV system. The topology of the 10-kV/1-MW SST is designed as a modular structure containing the dual active bridge (DAB) converter and full bridge...
An automatic, defect-oriented method is proposed for activating latent defects in analog and mixed-signal integrated circuits. Based on the topology modification technique, added stress transistors generate voltage stress that activates these latent defects. This contrasts with burn-in testing which uses increased temperatures as a fault activation mechanism. Moreover, this Design-for-Testability...
In this paper a method is presented to address the automatic testing of analog ICs. Based on Design-for-Testability building blocks offering extra controllability and extra observability, a test infrastructure is generated for a targeted circuit. The selection of the extra blocks and their insertion into the circuit is done automaticaly by a proposed optimization algorithm. Adopting a defect-oriented...
This paper addresses the important issue of fault tolerance in network-on-chip (NoC) and presents an on-the-field test and configuration infrastructure for a 2-D-mesh NoC, which can be used in many generic shared-memory many-core tiled architectures and MPSoCs. This paper also details all the hardware and software means needed to: 1) initialize the NoC in a clean state (self-deactivation of faulty...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
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