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Automated Complementary Metal Oxide Semiconductor (CMOS) logic circuit design leads to the reduction in costs associated with manpower and manufacturing time. Conventional methods use repetitive manual testing guided by Logical Effort (LE). LE provides an easy way to compare and select circuit topologies, choose the best number of stages for path and estimate path delay. In this paper, we propose...
Leakage power is a key challenge in VLSI design, and process variations have aggravated the problem. Interconnects have become very critical in modern VLSI designs and have started to play a major role in determining the power and performance of a design. Certain VLSI circuits such as FPGAs are interconnect dominated, such that their performance and power are largely governed by the interconnects...
With the CMOS transistors being scaled to sub 45 nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of flip-flops. First, it is shown that NBTI tightens...
This paper introduces a framework for the minimization of leakage power consumption of asynchronous circuits via using dual threshold voltages technique. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the circuit. We propose a heuristic method based on quantum genetic algorithm which finds the optimal high and low threshold voltage assignment. Experimental...
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and routing architectures are considered. For such explorations, it is not feasible to spend significant amounts of time on transistor-level design. This paper presents an automated transistor sizing tool for FPGA architecture...
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