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This paper presents a MOS-only high power supply rejection (PSRR) voltage reference with a very low temperature coefficient (TC) that consumes only tens of nano-Watt. It is composed by a threshold voltage monitor circuit with no resistors, cascaded with a thermal voltage generator, adequate for fabrication in standard processes. Since the MOS transistors operate in subthreshold and near-threshold...
In this paper, a simple and accurate circuit-simulator compact model for gallium nitride (GaN) high electron mobility transistor (HEMT) is proposed and validated under both static and switching conditions. A novel feature of this model is that it is valid also in the third quadrant, which is important when the device operates as a freewheeling diode. The only measurements required for the parameter...
In retargeting of a nano-watt CMOS reference circuit, we adopt an advanced compact MOSFET model to describe the drain current consistently in strong and weak inversion levels. Based on this model, we describe all bias conditions in terms of ratios of the channel widths and lengths. Taking the effect of very long channels into account, we formulate the threshold voltage as a function of the drain-source...
Hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT) have been important device in modern display panel production. In this paper, we study amorphous silicon thin-film-transistor (TFT) degradation under temperature and bias stresses. Rensselear polytechnic institute (RPI) model is widely used for circuit simulation of a-Si:H TFTs, but the temperature (T = −20 − +65°C) and bias stress...
When considering modern ICs mapped onto nanometer CMOS technologies, increasingly higher power densities and larger power density spatial gradients are well known to be the main source of thermal hot-spots, which in turn may cause huge performance variations, low-energy efficiency, and thus, low reliability. The resulting difficulties in managing temperature have become one of the major challenges...
Temperature effect is one of the critical factors in manufacturing variability which could affect the designed circuit. This paper presents a MOSFET mismatch model with the consideration of temperature variations using physical based SPICE model parameters. The model development includes the mismatch measurement at different temperatures and enhancement of standard device model card. Mismatch temperature...
This paper presents both static and dynamic NBTI Negative Bias Temperature Instability model based on the novel Reaction-Trapping theory. The accuracy of the proposed is greatly improved comparing to the classical Reaction-Diffusion theory, and the results agree well with the experiments over a wide range of temperature. Finally, the NBTI model of FinFETs is demonstrated through SRAM simulation.
Negative bias temperature instability (NBTI) has become an important cause of degradation in scaled PMOS devices, affecting power, performance, yield and reliability of circuits. This paper proposes a scheme to detect PMOS threshold voltage (VTH) degradation using on-chip slew-rate monitor circuitry. The degradation in the PMOS threshold voltage is determined with high resolution by sensing the change...
As mainstream processing technology advances into 65 nm and beyond, many factors that were previously considered secondary or insignificant, can now have an impact on chip timing. One of these factor is inversed temperature dependence (ITD). As supply voltage continues scaling into sub-IV territory, delay-temperature relationship can be reversed on some cells, meaning that device switching time may...
A physical yet analytical phase change memory (PCM) model simultaneously accounting for thermal and electrical conductivities is presented. Due to the physics based nature of the model, the essential temperature from heating and cooling of PCM during operation is instantaneously updated. More importantly, the model can be applied to non-conventional circuit design technique. We show that for the first...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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