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In high-voltage integrated circuits (HV-ICs) operating at high temperatures, the high electric field spreading out from the high-voltage bond-pad can induce charge transport phenomena in the encapsulation material. A new TCAD-based approach is proposed which is suitable for investigating the role played by the propagation of charge within the plastic mold over the surface of high-voltage circuits...
FaRBS (Failure Rate Based Simulation Program with Integrated Circuit Emphasis) is a new physics-of-failure based Very Large Scale Integration (VLSI) circuit reliability prediction method. With multiple failure mechanisms inh erently modeled and analyzed, FaRBS will make reliability engineers' life much easier by directly revealing each stress's acceleration effect at system level, thus helping reliability...
Negative bias temperature instability (NBTI) has become one of the major limiters for product lifetime, and various models have been proposed in order to explain NBTI. In this paper, an analytical model for DC NBTI and AC NBTI is proposed. This model describes the different time dependence of DC NBTI degradation at both short- and long-term stresses, and also reproduces the frequency and duty cycle...
This work presents a CDM circuit-level model for stacked die in a BGA package. Circuit simulation is used to investigate the voltage stress on the die-to-die interface circuits. The power net connections are found to impact the CDM reliability. An ESD protection scheme for the die-to-die interface circuits is proposed.
This paper demonstrates a deterministic, variability-aware reliability modeling and simulation method. The purpose of the method is to efficiently simulate failure-time dispersion in circuits subjected to die-level stress effects. A Design of Experiments (DoE) with a quasi-linear complexity is used to build a Response Surface Model (RSM) of the time-dependent circuit behavior. This reduces simulation...
Negative Bias Temperature Instability (NBTI) has become an important reliability concern for nano-scaled Complementary Metal Oxide Semiconductor (CMOS) devices. In this paper, we present an analysis of temperature impact on various sub-processes that contribute to NBTI degradation. We demonstrate our analysis on 90nm industrial design operating in temperature range 25-125?? C. The key temperature...
Strained Si is implemented into the standard CMOS process to enhance carrier transport properties since the 90 nm technology node. However, due to the non-uniform stress distribution in the channel, the enhancement of carrier mobility and threshold voltage strongly depend on layout parameters, such as channel length (L) and source/drain diffusion length (Lsd). In this work, a compact model that physically...
As the electronic industry is making its progress to miniaturize high performance, smaller and lower-priced IC packages, 3D packaging technologies are presently used to achieve these goals. Although 3D packaging technologies are vastly studied and applied to perform better performance, low power consumption and smaller packaging size of IC packages, thermo-mechanical problems occur as well due to...
3D integrated circuit technology is an emerging technology for the near future, and has received tremendous attention in the semiconductor community. With the 3D integrated circuit, the temperature and thermo-mechanical stress in the various parts of the IC are highly dependent on the surrounding materials and their materials properties, including their thermal conductivities, thermal expansivities,...
Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90 nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically...
Rapid heating and cooling are commonly encountered events in integrated circuit processing, which produce thermal shocks and consequent thermal stresses in wafers. The present paper studies the heat transfer in sapphire wafers during a thermal shock as well as the dependence of the wafer temperature on various process parameters. A three-dimensional finite-element model of a single sapphire wafer...
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