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Elementary mathematical functions are pervasively used in many applications such as electronic calculators, computer simulations, or critical embedded systems. Their evaluation is always an approximation, which usually makes use of mathematical properties, precomputed tabulated values, and polynomial approximations. Each step generally combines error of approximation and error of evaluation on finite-precision...
Multithread programming tools become popular for exploitation of high performance processing with the dissemination of multicore processors. In this context, it is also popular to exploit compiler optimization to improve the performance at execution time. In this work, we evaluate the performance achieved by the use of flags -O1, -O2, and -O3 of two C compilers (GCC and ICC) associated with five different...
In this paper, we propose a new architecture for automotive ECUs that incorporates security and dependability primitives with negligible performance, energy, and resources overhead. We implement our proposed ECU architecture on Xilinx Automotive (XA) Spartan-6 FPGA. We demonstrate the effectiveness of our proposed architecture using a steer-by-wire (SBW) application over controller area network with...
This work presents a comparison of two implementations of the last software version of The High Efficiency Video Coding (HEVC) decoder in a single low cost processor ARM Cortex-A series using NEON architecture which is a Single Input Multiple Data (SIMD). By using this technology of optimization, the whole execution time is reduced up to x4. We have analyzed separately all the blocks in the decoder...
High Efficiency Video Coding is the latest video standard aiming to replace H264/AVC standard by improving significantly the coding efficiency and the compression performance which allows HEVC to be mostly suitable for high-definition videos for multimedia applications. However, the encoding process requires a high computational complexity that needs to be alleviated. Hence, the paper proposes a software...
This paper describes a tool which enables source to source compilation. Implemented Polyhedral Source-to-Source Compiler (PSSC) is based on Polly compiler and LLVM infrastructure and it enables automatic recognition of parallel regions of C/C++ code and annotating them with OpenMP / OpenACC pragmas. The analysis of the input code is done by Polly compiler and then the results are mapped to original...
Arduino [1] is an open source platform that offers a clear and simple environment for physical computing. It is now widely used in modern robotics and Internet-of-Things (IoT) applications, due in part to its low-cost, ease of programming, and rapid prototyping capabilities. Sensors and actuators can easily be connected to the analog and digital I/O pins of an Arduino device, which features an on-board...
This paper first proposes the concept of architectural time predictability, which separates the time variation due to hardware architectural/microarchitectural design from that caused by software. We then propose a new metric — standard deviation of clock cycles per instruction (CPI), to measure architectural time predictability. Our experiments confirm that standard deviation of CPI is an effective...
Architecture Analysis and Design Language (AADL) is a standard that originated in the avionics domain, but is now being used in avionics and other critical distributed real-time embedded system design. AADL provides a formal notation and semantics for capturing an entire distributed platform architecture (hardware components, protocols, and software architecture annotated with properties including...
MIPS (Microprocessor without Interlocked Pipeline Stages) is an Instruction Set Architecture used in applications such as computers, routers, game consoles and various embedded systems. Among the advantages of this pattern, it could be cited the variety of free software such as compilers and simulators. This paper shows a methodology required to adapt other architectures to use a MIPS-1 instruction...
Open source development applied to cellular GSM technology is a fairly recent, but growing, concept. Another trend is the continually growing capability of low-power embedded processors, which makes them increasingly suitable for open source GSM applications. This paper applies two open source software packages, OpenBTS and OpenBSC, to an readily available embedded hardware platform, the Universal...
Processor design is a widely studied topic in computer system architecture design. How to improve computer performance is an important part of the computer overall design. In general processors, multiplication components play a decisive role in processor's performance. An important and frequent operation in decimal computations is multiplication. However, due to the inherent inefficiency of decimal...
This paper presents some work in progress on the design and implementation of efficient floating-point software support for embedded integer processors. We provide quantitative evidence of the benefits of supporting various non-generic (that is, fused, specialized, or paired) operations in addition to the five basic arithmetic operations: for individual calls, speedups range from 1.12 to 4.86, while...
Multiplication, as one of the four basic operations embedded in arithmetic processors, is nowadays experiencing being spotlighted by the hardware designers involved in the revived decimal arithmetic. The decimal hardware units usually employ the sequential implementation for this operation, due to the high area cost of the parallel decimal multipliers. However, the main drawback of this iterative...
This paper presents a Radix-100 divider based on decimal non-restoring and selection by truncation method. Two decimal quotient digits can be selected in each iteration, which can reduce half of the iteration cycles. Initialization is required to scale the divisor into a pre-calculated range, and also used for generating some multiples of the scaled divisor. Implemented with STM 90-nm standard cells...
High computational demands of today's wireless communication standards require the design of highly flexible Software Defined Radio (SDR) platforms like the OpenAirInter-face ExpressMIMO platform. A DSP engine of major importance is the Front-End Processor (FEP) which deals with the different air-interface operations at the transceiver side. In this paper we propose an Application Specific Instruction-Set...
This paper presents the Flexible Radio Kernel (FRK), a configuration and execution management environment for hybrid hardware/software flexible radio platform. The aim of FRK is to manage platform reconfiguration for multi-mode, multi-standard operation, with different levels of abstraction. A high level framework is described, to manage multiple MAC layers, and to enable MAC cooperation algorithms...
There is an increasing demand for converged solution for multi-standard radio processors to support existing and future standards. In this work, heterogeneous multi-processor platform is proposed for multi standard wireless communication system which is programmable and scalable in adapting to future standards. Channel decoding algorithms form important constituent of wireless communication system...
A Multiplierless Reconfigurable DFT/DCT Processor (MRP) design suitable for multicarrier applications is presented. The MRP implementation is based on a Reconfigurable Systolic Array (RSA) architecture that supports N-point DFT or DCT computations. All multiplication blocks in the MRP circuit have been implemented using the CSE-BitSlice technique to reduce hardware usage, and power consumption. Simulation...
An enabling concept of joint tactical radio system (JTRS) to provide global connectivity to the warfighter is the development of radio waveforms and applications that can be readily ported to different members of the JTRS radio family. Waveform porting is a pragmatic realization that ubiquitous plug-and-play is not possible for tactical radios possessing different hardware architectures and missions...
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