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This paper presents two circuits for implementing the restore operation of a non-volatile (NV) memory cell in which data from a programmable metallization cell (PMC) can be copied (restored) into a static random access memory (SRAM). In the first proposed design, a transmission gate is added to each row of cells of the memory array in which a concurrent error detection (CED) circuit is also present...
Resistive random access memory (ReRAM) has been demonstrated as a promising non-volatile memory technology with features such as high density, low power, good scalability, easy fabrication and compatibility to the existing CMOS technology. The conventional three-dimensional (3D) bipolar ReRAM design usually stacks up multiple memory layers that are separated by isolation layers, e.g. Spin-on-Glass...
A novel resistive memory with the TiN/Ti/HfOx/TiN stack is proposed and fully integrated with 0.18 μm CMOS technology. The excellent memory performances such as low operation current (down to 25 μA), low operation voltage (<;1.5 V), high ON/OFF resistance ratio (above 100), and fast switching speed (10 ns) have been demonstrated for this ReRAM. Moreover, the device exhibits excellent scalability...
A latch-type sense amplifier (SA) utilizing adaptive resistance technique is proposed. With adaptively adjusted resistance in a latch path, the proposed SA can compensate for an erroneous voltage drop in bit-lines induced by bit-cell leakage current. The simulation shows that the sense amplifier margin (SM) is improved in the presence of mismatches. The SA test chip is fabricated in a 0.18-μm CMOS...
This paper presents low power circuit design for voltage regulator and resistor to digital converter that are used in a RFID-like sensing circuit for measuring the resistance of a sol-gel sensor. The regulator circuit has simple circuit structure and consumes zero DC current (except the current drained by its load). The resistor to digital converter consists of a cascoded current mirror, a reference...
We present a negative-resistance read scheme and write scheme for spin-torque-transfer (STT) MRAM. A negative resistance shunting an STT-MRAM cell performs a non-destructive read operation, and saves power during write compared with the conventional scheme. Measurements show an 8 ns non-destructive read-access time and an average write power savings of 10.5% for a 16 kb STTMRAM fabricated in 0.13...
This paper analyzes the crystallization statistics and optimizes the performance of complex doped GST on 256 kb memory arrays in 180 nm CMOS technology. A novel method of deriving an optimized SET strategy from the RESET current distribution is developed. This significantly improves performance and results in 200 ns SET time. A large Rreset/Rset ratio can be maintained even after 8E6 cycles.
Three dimensional memory systems has been argued as a potential pathway in solving the ever growing difference between comparative speeds of CPU and memory systems. In this paper, we describe a three-tier, three-dimensional SRAM macro that has been designed and fabricated in a 0.18 um FD-SOI CMOS technology. 3D stacking is found to improve wire latency as compared to planar memory structure although...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
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