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This work proposes a new method for the extraction of the flatband voltage, effective nanowire width and doping concentration of junctionless nanowire transistors. The accurate extraction of such parameters is essential for the understating of the device behavior and for the prediction of its performance in circuits through analytical models. The method is validated using 3D numerical simulations...
P-channel solution-processed organic thin film transistors based on a dual layer semiconducting network of polythiophene polymers and oriented germanium nanowires show a marked enhancement of up to five-fold in hole field effect mobility with respect to that of pristine polythiophene devices. The work presented here furthers our understanding of the interaction between polythiophene and oriented nanowires...
This letter for the first time proposes a hybrid P/N substrate as a poly-Si p-channel for junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structures. The hybrid P/N JL-TFT exhibits a high $I_{\mathrm {\mathrm{{\scriptstyle ON}}}}$ /$I_{\mathrm {\mathrm{{\scriptstyle OFF}}}}$ current ratio (> 107), a steep subthreshold swing of 64 mV/dec, and a low drain-induced barrier...
Zinc oxide was directly grown on the graphene layer by the hydrothermal synthesis method, and the field emission property of this hybrid structure was tested by a diode structure device. Compared with the Zinc oxide directly grown on the silicon substrates, the hybrid emitter shows better performance in the field emission properties, including low turn-on field, threshold field and high emission current...
The authors discuss the 3-D and 2-D X-on-Y (XoY) assembly techniques, utilizing specific examples to illustrate the potential of these methods for the fabrication of high performance devices on arbitrary substrates. For fabrication of 3-D structures, a templated nanomaterial growth technique is used. Specifically, anodic aluminum oxide (AAO) is used as the growth template. Alternatively, for 2-D assembly,...
In this study, we have proposed a simple but novel way to fabricate poly-Si NW-SONOS devices. With a slight modification in the fabrication procedure, three types of devices having various gate configurations (SG, ΩG, and GAA) were successfully fabricated and characterized. The experimental results unambiguously show that, owing to the superior gate controllability over NW channels, much improved...
Among the wide range of interesting potential applications for nanowires (NWs) of semiconducting oxides, we have focused our attention on the sensing properties of SnO2 NWs. SnO2 NWs networks were prepared using evaporation/condensation technique. The morphology, crystalline structure, and composition of nanowires structures were investigated using scanning and transmission electron microscopy, and...
Recent experimental results on Si nanowire MOSFETs are presented. The devices were fabricated in a top-down approach on unstrained and biaxial strained SOI substrates exhibiting good I-V characteristics with Ion/Ioff-ratios of 107 and off-currents as low as 10-13 A. Subthreshold slopes of about 70 mV/dec for SOI n- and p-FETs and 65 mV/dec for strained SOI n-FETs were obtained. The on-current and...
This work has developed techniques for fabrication of gated field emission device using ZnO nanowires (NWs) based on both microfabrication techniques and low temperature (~80 degC) solution grown method.
In summary, as we move it 15 nm and beyond, it is critical that the device structure fit in ever smaller footprint. It seems that Si devices can fulfill this key requirement: moving from thick body devices to thin body and ultimately to Si nano-wires, in order to enable small gate length devices. This is the good news. Better news could be if we are able to find a device that can do better than Silicon...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
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