The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Phase-locked loops (PLLs) are doubtless the most popular synchronization technique in the power converters. Almost all proposed PLL structures known in literature are inherently nonlinear and can be linearized as second order linear time invariant system. Nonlinear nature of PLLs degrades their performances, and question arises if there exist an enhanced PLL structure that would have superior performances...
This paper proposes a method to implement the modified square loop digitally on the FPGA to solve the problem, that the divide circuit in the traditional square loop is difficult to achieve. The modified square loop has a similar structure to the traditional square loop. The method of modified square loop is to multiply quadrature output together to replace the divide circuit. In this paper, a specific...
The evolution of wireless technology to its fourth generation has improved exponentially from its predecessor. On the other hand, this improvement requires a higher level of complexity and computation to process the signal. In this paper, we propose an architecture for 4G LTE's time domain baseband signal processor. To improve the computation time so that it meets the real-time specification, we propose...
A Hardware Trojan is a malicious hardware modification of an integrated circuit. It could be inserted at different design steps but also during the process fabrication of the target. Due to the damages that can be caused, detection of these alterations has become a major concern. In this paper, we propose a new resilient method to detect Hardware Trojan based on path delay measurements. First, an...
The use of Field Programmable Gate Array (FPGA) hardware in Test Program Set (TPS) development is highly beneficial due to its ability to be reconfigured on the fly to simulate various ATE instruments or unique signals generated from discrete hardware components. FPGA hardware can by utilized for creating an array of synthetic instruments; and by utilizing a FPGA, a single piece of hardware can be...
This paper presents the implementation of curve on FPGA circuit (Field Programmable Gate Array) Spartan 3 of Xilinx, it based on Taylor approximation by segment, used third order polynomial in order to reduce the maximum error. First of all, we have stocked all coefficients, computing with Mat lab tool, in the block memory. After that, an architecture is proposed and implemented under ISE9.2i environment...
Several solutions for implementing Petri net models on FPGA thanks to a transformation in a VHDL code have been proposed in literature. But none deals with the management of transition conflicts in the specific case of synchronous implementation of interpreted Petri nets. This article presents an automatic method to deal with conflicts from their detection to their implementation on FPGA. One solution...
Among the OFDM synchronization algorithms, the algorithm based on repeated structured training sequence is widely used because of its simple structure and high accuracy of frequency estimation. An implementation method of OFDM timing synchronization with repeated-structured training sequence is presented in this paper, which uses FPGA as a hardware platform. There are three parts in this design. The...
Available simulators for testing Hardware Descriptive Language (HDL) codes provide output with respect to simulator clock. This output is not sufficient for the analysis of Field Programmable Gate Array (FPGA) based embedded controllers. The embedded controllers give actuation signal to the plant and receives plant output as the feedback signal. Therefore a coupling between embedded and plant simulators...
The most important logic unit in asynchronous circuit is null conventional logic unit. A new technology called semi-static threshold gate is used for realization of null conventional logic unit. In this paper TH23 NCL gate is designed in both semi-static and static style. These are implemented in tsmc 180nm process with minimum 1.8V power supply. Power analysis is performed for both type of style...
The paper presents an original theory of computing infrastructure, which is quasi-holographic-element system theory. Based on this theory, a new type model that is quasi-holographic element mathematical model is formed. It reflects kinds of operation relations of number. The characteristics of the new model check and store going the same way, synchronization of compute and check, integrative store...
Most of the Power Quality Analyzers & impulse recorders available in the market do not have the capability to be integrated with another equipment in a flexible manner, as they are specifically designed for single user applications. Analyzers with remote network monitoring capability are extremely expensive. This paper describes flexible and low cost embedded system architecture for remote power...
In this paper, we propose a hardware implementation of a Feed-Back Chaotic Synchronization (FCS) for designing a real-time secure symmetric encryption scheme. This proposed scheme allows for the design and implementation of real time synchronization between two embedded chaotic generators for secure communications. The implementation and experimental results mapped on two Xilinx FPGA Virtex technology...
In conventional static implementations for correlated streaming applications, computing resources may be in-efficiently utilized since multiple stream processors may supply their sub-results at asynchronous rates for result correlation or synchronization. To enhance the resource utilization efficiency, we analyze multi-streaming models and implement an adaptive architecture based on FPGA Partial Reconfiguration...
This paper describes a Field Programmable Gate Array (FPGA) implementation of a Digital Front End (DFE) block for a Multi-Carrier Multi-Antenna (MCMA) system. The decimation/ interpolation filters used for obtaining the required channel bandwidth are split into several low order decimation/ interpolation stages, each of them being implemented as a polyphase filter. At the receiver, the DFE contains...
This paper presents the design of synchronizer hardware for DVB-T receiver. The main function of synchronizer is to detect and compensate the time offset and frequency offset which happen during transmission as well as frame start detection. Proposed synchronizer utilizes cyclic prefix of OFDM signals. The design includes computational bit precision modeling, architecture design, register-transfer-level...
This paper proposed a RFID base-band transmission model based on the analysis of RFID base-band communication course, in which FPGA technology is employed to design a communication IP core, integrating functions of base-band encoding & decoding and data transmitting. The RTL design of base-band communication IP core based on modular method is also presented. The experimental studies based on Quartus...
This paper studies impulsive synchronization of digital chaotic PN (Psudo-noise) sequences. A new continuous chaotic system which is constructed based on Sprott system, is used to generate the PN sequences via FPGA (Field Programmable Gate Array). Moreover, FPGA technology is also applied to realize the impulsive synchronization between two PN sequences by the chips of Altera Cyclone II EP2C35F484C8...
The paper presents hardware efficient design of digital signal processing (DSP) based bit synchronizer and lock detector circuit for bi-phase data. The system is developed for one of the payload of Chandrayaan-I mission, and tested for its performance. Apart from the implementation, paper describes the mathematical modeling of bit synchronizer. The whole design is accommodated in a single Actel-1280...
This article presents the design of a baseband processor for software radio, which uses carrier synchronizer and bit detector-synchronizer circuits based on algorithms implemented in hardware, and an inverse tangent circuit based on the CORDIC algorithm. In this case, the functional blocks of the processor can be reconfigured to support multiple modulation formats and signal processing tasks in the...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.