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A broad range of physical phenomena in science and engineering can be explored using finite difference and volume based application codes. Incorporating Adaptive Mesh Refinement (AMR) into these codes focuses attention on the most critical parts of a simulation, enabling increased numerical accuracy of the solution while limiting memory consumption. However, adaptivity comes at the cost of increased...
Large-scale Atomic/Molecular Massively Parallel Simulator (LAMMPS) code was examined in an Intel Quad-Core Xeon platform for its speedup and scaling ability. The study shows that the most time-consuming task in the code is force computing and this part can be scaled linearly. However, other tasks do not have this feature. Future work will focus on speeding up of these other parts to enhance the performance...
The trend towards heterogeneous multi-core integration and higher communication bandwidth drastically increases the complexity of the SoC. Architecture design and system validation become extremely challenging. This paper presents a system-level virtual platform and simulation environment for multi-core system performance profiling and evaluation. At the higher level of abstraction, we implement a...
In this paper, using the Intel multicore architectures and the emerging multiview video coding standard, we introduce a framework for performing analysis, simulation, and evaluation of heuristics scheduling algorithms for implementing computationally intensive algorithms on multicore processors. The framework allows for accurate and quantitative characterization of the performance of dynamic scheduling...
Performance evaluation techniques for fundamental graphics algorithms and for algorithms to be used in multimedia and embedded systems are investigated. Models of computation considering only arithmetic and logic operations taken on input data are regarded as inadequate for processors with instruction-level parallelism. For experimental evaluation of graphics algorithms clock-cycle counting is found...
Presents an approach that has been proposed in order to investigate the workload balance problems in a simulator of the Wolf parallel architecture, known as Saw (Simulator of Architecture Wolf). This approach can be applied to the simulator in order to eliminate overloaded and underloaded units observed during the first experiments on the Wolf architecture. The unexpected results obtained are well-understood...
It is essential to extract fine grain parallelism for further increase of processor performance. This paper investigates an extension model of VLIW architecture called V++, which retains the capabilities of VLIW architecture to effectively exploit fine grain parallelism while introducing facilities for restructuring very long instruction words dynamically. V++ adopts two types of restructuring methods:...
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