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This paper presents the analysis and design of high speed, high gain fully differential operational amplifier(op-amp). The op-amp is designed for sample and hold circuit of 14 bit 100 MS/s pipelined analog-to-digital converter (ADC). Both the main op-amp and the boosting op-amp are fully differential folded-cascode. The main op-amp has a switched capacitance common mode feedback circuit. The boosting...
A sample/hold (S/H) circuit for a 14 bit 100 MSample/s analog-to-digital converter is implemented and optimized. High performance gain-boosted folded-cascode opamp (GBFCA) and bootstrapped switches are used to maximize SNDR and SFDR of the S/H circuit. An optimal design criterion is developed to find the best solution giving the shortest settling time. After eliminating the slow-settling component...
This paper presents a design tool for the synthesis of pipeline ADCs which is able to optimally map high-level converter specifications, such as the required effective resolution, onto electrical-level parameters, i.e., transistor sizes and biasing conditions. It is based on the combination of a behavioural simulator for performance evaluation, accurate models of the converter components, and an optimization...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
This paper presents the circuit implementation of a reconfigurable Analog to Digital Converter (ADC) for UWB and Bluetooth communication standards for mobile terminals. The bandwidth accuracy space is covered through smart configuration of a flexible capacitive interpolation ADC, used as stand-alone in UWB mode and as quantizer of a Sigma Delta ADC in Bluetooth mode. The ADC has been accurately modeled...
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