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This paper reports a new scalable behavioral modeling technique for novel nano crossbar ESD protection structures using Verilog-A language. Accurate models for nano crossbar ESD protection structures with different sizes were developed, which were validated by circuit level simulation and transmission line pulsing ESD measurement.
Logic synthesis of reversible circuits has received considerable attention in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely single missing-gate...
This paper presents a c-testable motion estimation (CTME) design to efficiently detect the faults in process elements (PEs). The goal of the CTME design is to offer high reliability for video coding systems. The proposed CTME was carried out by Verilog HDL and synthesized with the TSMC 0.18 mum CMOS technology. Logic simulation results show that the proposed CTME guarantees 100% fault coverage with...
Level-testability of multi-operand adders consisting of carry save adders is shown by showing test design for them. A multi-operand adder is a main part of a multiplier. 6L+2 patterns are sufficient to test a multi-operand adder under cell fault model, where L denotes the depth of the multi-operand adder. A test method of the multi-operand adder used as a partial product compressor in a multiplier...
The continued increase of the integration density of systems on chip (SoCs) and the number of embedded memory blocks in them, together with the continued technology scaling, increases their sensitivity to a variety of potential manufacturing (new) defects. Standard march tests are usually used to achieve a good fault/defect coverage. This paper presents an experiment in diagnosing defects in the circuitry...
Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing, a particularly...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
In this paper, we investigate optimum radiation hardened by design (RHBD) for use against single-event transients (SET) using low-pass filters (LPF) including RHBD techniques against single-event upsets (SEU) for sequential logic in 45 -nm technology in a terrestrial environment. Three types of LPF were investigated regarding their SET pulse immunities, area penalties, and performance penalties. We...
The field of electronic noses and gas sensing has been developing rapidly since the introduction of the silicon based sensors. There are numerous systems that can detect and indicate the level of a specific gas. We introduce here a system that is low power, small and cheap enough to be used in mobile robotic platforms while still being accurate and reliable enough for confident use. The design is...
This paper concerns the evaluation of performance of grid-connected PV inverters in terms of conversion efficiency, European efficiency, static and dynamic MPP efficiency. Semi-automated tests were performed in the PV laboratory of the Institute of Energy Technology at the Aalborg University (Denmark) on a commercial transformerless PV inverter. Thanks to the available experimental test setups, that...
Recently, a systematic procedure is proposed to derive a minimum space quantum circuit for a given classical logic with the generalized quantum Toffoli gate which is universal in classical boolean logic. Since quantum computation is reversible, we can use this property to build quantum iterative logic array (QILA). QILA can be easily tested in constant time (C-testable) if stuck-at fault model is...
Straight line programs in which array elements can be referenced and set are considered. Two programs are equivalent if they compute the same expression as a function of the inputs. Testing the equivalence of programs with arrays is shown to be NP-complete, while programs without arrays can be tested for equivalence in linear time. Equivalence testing takes polynomial time when programs have either...
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