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This paper presents an accurate resistance characterization technique for magnetic random access memory (MRAM), such as STT-MRAM. By annulling the mismatch effect of CMOS transistors, this technique produces a resistance distribution profile of MRAM devices in a large array that reflects the actual device statistics. A 1 Kb array of MTJs with an intrinsic 3σ low resistance state distribution modeled...
In this paper, we describe a six-transistor static random access memory (SRAM) cell optimization methodology for transistors with significantly improved matching, while maintaining compatibility with the baseline design. We briefly describe the reduced AVT transistors and show that they allow substantially improved minimum SRAM operating voltage (Vmin) and improved array leakage. Using an efficient...
A low power SRAM macro is customized in 90nm TSMC model technology. The design minimizes the area of the bitcells to achieve a total area of 0.370 mm2. A dynamic supply voltage management scheme is used to reduce the leakage power in the standby mode. The 64 kbits sub-array operates at 1.54 GHz for 1.0V supply voltage. Monte carlo simulation results show that the macro has a 6% failure probability...
This paper examines the read stability, write ability and leakage power of various dual-Vt configurations, of an asymmetric SRAM cell (pass cell) in an array considering the process-induced intra-die threshold voltage variations using N-curve metrics. The effects of process induced Vt variations in 22 different dual-Vt cell combinations are evaluated and compared using Monte Carlo simulations. The...
Process variation poses a threat to the performance and reliability of the 6T SRAM cell. Research has turned to new memory cell designs, such as the 3T1D DRAM cell, as potential replacement designs. If designers are to consider 3T1D memory architectures, performance models are needed to better understand memory cell behavior. We propose a decoupled approach for collecting Monte Carlo HSPICE data,...
We present an analysis of offset voltage and noise in a dynamic comparator. To limit the offset and noise to acceptable levels, a single comparator must be sized quite large. We show that better use can be made of this die area by dividing it into an array of redundant comparators from which the lowest-offset device is chosen. Monte Carlo simulations with a 45 nm CMOS process confirm that the input-offset...
We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. In addition, we introduce a new concept, "quality of a bit (QoB)" for it. The dependable SRAM has three modes (normal mode, high-speed mode, and dependable mode), and dynamically scales its reliability and speed by combining two memory cells for one-bit information (i.e. 14T/bit)...
We have reduced the mismatch error in a bio-inspired vision sensor, of the kind that is popularly known as dasiaoctopus retinapsila. Mismatch and noise reduction techniques developed for traditional imagers, like correlated double sampling (CDS), cannot be applied to this frame-free asynchronous vision sensor. In an dasiaoctopus retinapsila, each self timed pixel integrates photo current until a threshold...
In this paper, we investigate optimum radiation hardened by design (RHBD) for use against single-event transients (SET) using low-pass filters (LPF) including RHBD techniques against single-event upsets (SEU) for sequential logic in 45 -nm technology in a terrestrial environment. Three types of LPF were investigated regarding their SET pulse immunities, area penalties, and performance penalties. We...
We study multi-bit upsets (MBU) in 65 nm SOI SRAMs. Proton beam and thorium foil experiments demonstrate that SOI SRAMs have lower soft error rate than bulk SRAMs. Monte Carlo SER simulations show that SOI SRAMs have a lower fraction of MBU than bulk SRAMs. The probability of MBU correlates with the spacing of sensitive devices in neighboring cells.
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