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Because of the high computation demand for multimedia applications like video decoding, there is a need to develop flexible and high performance reconfigurable computing architectures. Taking video decoding algorithm as an example, we propose a reconfigurable computing realization solution of multimedia application. Based on the analysis of parallelism in video decoding algorithm, a hardware platform...
A digital phase-locked loop (DPLL) is designed using 0.18 mm CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz-1 GHz. The DPLL operation includes two stages: (i) a novel coarse-tuning stage based on a flash algorithm, and (ii) a fine-tuning stage similar to conventional DPLLs. The flash portion of the DPLL is made up of frequency comparators, an encoder and a decoder...
In this paper, we propose a parallel hybrid merge-select sorting approach for the implementation of K-best list sphere detection (LSD) multi-input multi-output (MIMO) decoder based on a recently developed novel Reconfigurable Instruction Cell Array (RICA). Several popular sorting algorithms adopted in MIMO decoding are analyzed and mapped onto our proposed platform. We discuss the targeted K-best...
The goal of this paper is to reduce the power and area of the Static Random Access Memory (SRAM) array while maintaining the competitive performance. Here the various configuration of SRAM array is designed using both the six-transistor (6T) SRAM cell and a new loadless four-transistor (4T) SRAM cell in deep submicron (130nm, 90nm and 65nm) CMOS technologies. Then it is simulated using HSPICE to check...
Turbo convolutional codes (TCC) are excellent error correcting codes as they show near Shannon capacity performance in communication systems. However, turbo decoders are computationally complex. Recently, a class of modified turbo codes called low complexity hybrid turbo codes (LCHTC) is proposed with bit error rate (BER) which is almost same as that of turbo codes. In this paper improved low complexity...
This paper proposes a full custom design of a 9-write and 17-read multi-port register file. The proposed register file can fulfill one read-after-write access in one system cycle with a synchronous read and an asynchronous write. The design employs a single-ended sense amplifier and a high-speed SCL address-decoder as write decoder controlled by VCLK, which is generated through a novel positive edge...
Breaking with the traditional modular architecture in which compression and cryptography are carried out separately, we propose an analysis-by-synthesis approach that exploits the properties of source codes to ensure a prescribed level of protection with manageable computational complexity. To illustrate the power of this methodology, we show that carefully inducing catastrophic errors in Huffman...
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