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This paper proposes the use of parameterised FPGA configurations for a new test set generation approach. The time-consuming problem of test set generation aims at finding the right input values to fully test an ASIC design. Since well-known methods for test set generation such as fault simulation techniques have become impractical to use due to their speed limitations, FPGAs have been used in order...
To meet the needs of the generalization and miniaturization of the automatic testing system, a new configurable test instrument was designed. The module had 32 input channels and 8 output channels. Each of the 32 channels could be configured as an analog measurement, digital measurement, frequency measurement or DMM; and each of the 8 output channels could be configured as a DC output or arbitrary...
This paper presents a multi-function multi-GHz test module designed to enhance the performance capabilities of automatic test equipment (ATE). The test module is designed with a core logic block consisting of a high-performance FPGA. It also contains an application specific logic block that is designed to perform multiple functions not possible with the FPGA alone. We demonstrate five applications:...
The recent trend of reconfigurable hardware and convergence of hardware platform in embedded system have enhanced the application of FPGAs. Although the capability and performance of FPGA have advanced, the testing of FPGAs both online and off-line (manufacturer oriented testing) poses a major challenge. Importance of delay testing has grown especially for high-speed circuits. Even presence of small...
In this paper we introduce a fine-grain fault diagnosis approach for reconfigurable logic blocks. As opposed to previous works, we propose to reuse rather than to discard defective blocks. We describe methods to analyze deeper a defective Xilinx Virtex2Pro slice and diagnose the fault, out of a set of 150, that causes the malfunction. The outcome of the fault diagnosis is subsequently used to characterize...
In this paper, we present a test pattern generation method based on fault injection for logic elements of FPGAs (Field Programmable Gate Arrays). This method is able to perform fault diagnosis for stuck-at-0 and stuck-at-1 faults, which can locate logic resource faults in the logic elements of FPGA. We use EP2C8Q208C8N's LE (Logic Element) of Altera as the object to generate the test pattern, work...
Reversible logic is attracting the researchers attention for fault susceptible nanotechnologies including molecular QCA. In this paper, we propose concurrently testable FPGA design for molecular QCA using conservative reversible Fredkin gate. Fredkin gate is conservative reversible in nature, in which there would be an equal number of 1s in the outputs as there would be on the inputs, in addition...
A built-in self-test (BIST) approach is presented for the configurable logic blocks (CLBs) in Xilinx Virtex-5 field programmable gate arrays (FPGAs). A total of 17 configurations were developed to completely test the full functionality of the CLBs, including distributed RAM modes of operation. These configurations cumulatively detect 100% of stuck-at faults in every CLB. There is no area overhead...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
We propose a built-in scheme for generating all patterns of a given deterministic test set T. The scheme is based on grouping the columns of T, so that in each group of columns the number ri of unique representatives (row subvectors) as well as their product R over all such groups is kept at a minimum. The representatives of each group (segment) are then generated by a small finite state machine (FSM)...
The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this...
Built-in self test (BIST) and built-in self repair (BISR) techniques have been developed for memory blocks in recent years. Such techniques are suited to enhance production yield, but also to facilitate long-term dependable circuits though self repair in the field of application. BISR for logic circuits has shown to be much more complex, for which only a few approaches have been published so far....
In this paper, we present a novel technique for online testing of feedback bridging faults in the interconnects of the cluster based FPGA. The detection circuit will be implemented using BISTER configuration. We have configured the Block Under Test (BUT) with a pseudo-delay independent asynchronous element. Since we have exploited the concept of asynchronous element known as Muller-C element in order...
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