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With recent advances and demands for data storage, new architectures for data controller chips are picking pace. Accordingly, the test methodologies for such chips are also becoming crucial since the large shipping volumes of those chips demand very few field returns. Along with the advances there is a need for a robust test strategy with some novel techniques which can be enabled to test the SOC...
As distributed systems such as automotive, medical, manufacturing automation become larger and more complex, it is difficult to test these systems. Also, the synchronization of distributed applications make the testing more difficult. In the Software-in-the-Loop (SiL) simulation, a synchronization method among clock of applications is provided for virtual hardware devices and environment. A typical...
This research describes an approach to test metastability of flip-flops with help of multiple at speed capture cycles during path delay test. K longest paths starting from a flip-flop are generated, such that a long path on one clock cycle feeds a long path on the next clock cycle, and so on. This permits the testing of flip-flop metastability and time-borrowing latches, that cannot be tested by any...
Clock skew minimization is an important design consideration. However, with the advance of the technology and the smaller device scaling, Process, Voltage, and Temperature (PVT) variations make the clock skew minimization face great challenges. To mitigate the impact of PVT variations, many previous works proposed the Post Silicon Tuning (PST) architecture to dynamically balance the skew of a clock...
The paper deals with the problem of test data volume, decompressor hardware overhead and test application time of scan based circuits. Broadcast-based test compression techniques can reduce both the test data volume and test application time. Pattern overlapping test compression techniques are proven to be highly effective in the test data volume reduction and low decompressor hardware requirements...
With the exponential increase of transistor counts, scan design encounters several problems such as large test data volume, long test application time and high test power. In this paper, we propose a new method to reduce test data volume, test application time and also average and peak power during test. The proposed method is based on a scan chain disabling technique where only one internal sub scan...
The practice of initializing a board or system for testing purposes is not an exact science, but rather, pursued empirically and with little help from IC designers. This paper examines some of the issues and trends that justify adding features to IEEE 1149.1 that will facilitate safe, fast and effective initialization of a board or system, to get it ready for testing and to leave it in a safe state...
This paper proposes a novel power-aware scan architecture: DCScan. In this architecture, the compatible scan cells are grouped into the same segment. Test data propagation in DCScan includes two parts: data copying and data shifting. There is no scan shift-in transition during data copying. Experimental results show our approach can achieve low test power, low wiring overhead and low test response...
We propose a built-in scheme for generating all patterns of a given deterministic test set T. The scheme is based on grouping the columns of T, so that in each group of columns the number ri of unique representatives (row subvectors) as well as their product R over all such groups is kept at a minimum. The representatives of each group (segment) are then generated by a small finite state machine (FSM)...
The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this...
Process scaling is well know to increase overall chip-level soft error rates (SER) if no additional mitigation techniques are applied [Seifert04]. The purpose of this study is to summarize recent investigations conducted by the author to characterize the SER benefits and limitations of one particular SER mitigation technique: radiation hardened sequentials that utilize local redundancy. The studied...
Encryption algorithms could suffer fault injection attacks in order to obtain the secret key. In this paper, a specific protection for any round-based encryption algorithm is presented, analyzed and tested. It is providing a high degree of robustness together with a small penalty in the algorithm throughput when dealing with specific intentional attacks. Experimental results on advanced encryption...
The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed...
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing - a delay overlapping stage...
Generally, the code excited linear predictive (CELP) coding is known as one of the best algorithms for bit rate between 4 kbps and 16 kbps. Recently, the algebraic CELP (ACELP) algorithm has been widely adopted in standard speech coders such as G.729 and Adaptive multi rate (AMR) and AMR Wide Band (AMR-WB).In order to improve the speech quality based on CELP algorithm, harmonic Pitch pre-emphasis...
This paper presents a course model for teaching component-based software development (CBSD) in the software engineering undergraduate curriculum to deepen and broaden student comprehension of component software. All hands-on lab practices are designed with open-source software tools. The course endows students the precious experiences of making design decisions via comparative study, risk analysis,...
Due to the increasing complexity of Web systems, security testing is becoming a critical activity to guarantee the respect of such systems to their security requirements. To challenge this issue, we rely in this paper on model based active testing. We first specify the Web system behavior using IF formalism. Second, we integrate security rules -modeled in Nomad language- within this IF model using...
In this paper we discuss the use cases for monitoring of Web services for compliance with policies and service level agreements. In particular, the quality of service associated with Web service interactions and its monitoring rely on the proper use by both parties of related Web service protocols. This monitoring is best served by an event-centric model and an extensible scripting language, such...
MPSS simulates the behavior of a high traffic transaction processing system. An effective use of MPSS is the analysis of the impact of exclusive control of system resources over multiple processes. MPSS consists of a control process and multiple application processes. The control process is designed to simulate a transaction processing monitor. It initiates and oversees multiple application processes...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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