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This paper investigates the impact of inter- and intra-die variations on binary and high-radix adders that adopt the borrow-save encoding. High-radix adders have been employed for the recoding of multipliers and for determining quotient and root digits in iterative division and square-root algorithms. These adders have been found to outperform conventional ripple-carry and carry-skip adders in certain...
The path delay fault model is effective in detecting small delay defects. The proposed approach identifies the delay behavior of paths in various circuit instances without enumerating them. It selects critical paths through path implicit operations on a compact data structure potentially containing an exponential number of path candidates. The experimental analysis on some of the largest ISCAS-89...
Accurately estimating the failure region of rare events for nanoscale analog circuit blocks under process variations is a challenging task. In this paper, we propose a new statistical rare event analysis method. The new method is based on the iterative failure region locating scheme to reduce the sample counts while still maintains estimation accuracy. We derive the complete formulation for failure...
With the advent of deep submicron CMOS technology, process parameter statistical variations are increasing resulting in unpredictable device behaviour. The issue is even aggravated by low power requirements which are stretching transistor operation into near/sub threshold regime. Consequently, traditional delay models fail to accurately capture the circuit behaviour. In view of this we introduce an...
In its simplest form, a parameterized block based statistical static timing analysis (SSTA) is performed by assuming that both gate delays and the arrival times at various nodes are Gaussian random variables. These assumptions are not true in many cases. Quadratic models are used for more accurate analysis, but at the cost of increased computational complexity. In this paper, we propose a model based...
Domino CMOS logic circuits are widely used these days in the design of high-performance modules in modern day integrated chips and microprocessors. The feature of high speed and less area overhead of these logic circuits compared to other logic styles make them a popular choice in the design of high speed circuits. As power consumption is directly proportional to the dynamic node capacitance, a new...
Effects of fluctuations in circuit timing due to process and environmental variations are becoming increasingly important as we move into sub-45 nm technology. Since the delay of each gate is dependent on its input vectors, the timing yield, the probability that the circuit meets the given timing constraint, varies with different primary input patterns. Traditional timing yield estimation approaches...
Dynamic power dissipation of a CMOS VLSI circuit depends on the signal activity at gate outputs. The activity includes the steady-state logic transitions as well as glitches. The latter are a function of gate delays, which, for modern VLSI circuits, have wide process-related variations. Both average and peak power dissipation are useful and are traditionally estimated by Monte Carlo simulation. This...
This work is concerned with carbon nanotube diameter variations and the resulting uncertainties on the behavior of logic gates made from single walled carbon nanotubes (SWCNTs). Monte Carlo simulations were performed for logic gates based on CNTs of different mean diameters using the Stanford CNFET model. Delay characteristics of logic gates (NOT, NAND, NOR) are studied. This work reveals that logic...
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