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In this paper, we explore the pessimistic voltage guardbands of two multicore x86-64 microprocessor chips that belong to different microarchitectures (one ultra-low power and one high-performance microprocessor), when programs are executed on individual cores of the CPU chips. We also examine the energy and temperature gains as positive effects of lowering the voltage in both chips while preserving...
This paper examines hardware trojan threats to semiconductor chips, which is particularly important for chips intended for vital infrastructure and critical applications. The phases of the chip production life-cycle are considered in terms of the opportunities for trojan insertion. Trojans are examined based on eight attribute categories. A matrix identifying the relationships between these attributes...
Defect density and variabilities in values of parameters continue to grow with each new generation of nano-scale fabrication technology. In SRAMs, variabilities reduce yield and necessitate extensive interventions, such as the use of increasing numbers of spares to achieve acceptable yield. For most microprocessor chips, the number of SRAM bits is expected to grow 2× for every generation. Consequently,...
In this paper, we present a software approach for localization of faulty components in a 2D-mesh Network-on-Chip, targeting fault tolerance in a shared memory MP2SoC architecture. We use a pre-existing and distributed hardware infrastructure supporting self-test and de-activation of the faulty components (routers and communication channels), that are transformed into “black hole”. We detail the software...
Internet of Things is a key component of next generation information technology. And the key of Internet of Things is RFID. Now Internet of Things brings new requirements to handheld UHF RFID reader. This paper proposed a complete solution of handheld UHF RFID reader based on AS3991 and AM3517 for The Internet of Things. This reader uses AS3991 UHF RFID reader chip , which conforms to ISO18000-6C...
Customized application-specific processors called ASIPs are becoming commonplace in contemporary embedded system designs. Neural networks are an interesting application for which an ASIP can be tailored to increase performance, lower power consumption and/or increase throughput. Here, both the bidirectional associative memory and hopfield auto-associative memory networks are run through an automated...
In this paper we present the Make And Take(MAT) approach for adding switch-mode power supply (SMPS) control to hard real-time systems. MAT enables control of the SMPS with the task scheduler and this allows the designer to use a less expensive and smaller (but noisier) SMPS without it affecting circuits sensitive to electromagnetic interference (EMI) such as high-impedance input signals and amplifiers...
Analytical processor performance modeling has received increased interest over the past few years. There are basically two approaches to constructing an analytical model: mechanistic modeling and empirical modeling. Mechanistic modeling builds up an analytical model starting from a basic understanding of the underlying system - white-box approach - whereas empirical modeling constructs an analytical...
For higher processing and computing power, chip multiprocessors (CMPs) have become the new mainstream architecture. This shift to CMPs has created many challenges for fully utilizing the power of multiple execution cores. One of these challenges is managing contention for shared resources. Most of the recent research address contention for shared resources by single-threaded applications. However,...
This work discussed how source and microarchitectural level characteristics correlate with processor temperature. The first look is at correlations between phase changes and temperature changes, which shows that the relationship between phases and temperature are consistent across architectures but that code selection by the compiler can have an impact on phase lengths and temperature behaviors. Understanding...
We demonstrate a hardware implementation of a complex event processor, built on top of field-programmable gate arrays (FPGAs). Compared to CPU-based commodity systems, our solution shows distinctive advantages for stream monitoring tasks, e.g., wire-speed processing and predictable performance. The demonstration is based on a query-to-hardware compiler for complex event patterns that we presented...
The instruction cache is a critical component in any microprocessor. It must have high performance to enable fetching of instructions on every cycle. However, current designs waste a large amount of energy on each access as tags and data banks from all cache ways are consulted in parallel to fetch the correct instructions as quickly as possible. Existing approaches to reduce this overhead remove unnecessary...
Since target applications in embedded systems are limited, we can optimize its cache configuration. A very fast and exact cache simulation algorithm, CRCB, has been recently proposed. CRCB assumes LRU as a cache replacement policy but FIFO- or PLRU-based cache is often used due to its low hardware cost. This paper proposes exact and fast L1 cache simulation algorithms for PLRU- or FIFO-based caches...
Multi-core system is becoming the next generation embedded design platform. Heterogeneous and homogeneous processor cores integrated in Multiple Instruction Multiple Data (MIMD) System-on-a-Chip (SoC) to provide complex services, e.g. smart phones, is coming up in the horizon. However, distributed programming is a difficult problem in such systems. Today, only in very few MIMD SoC designs we can find...
This paper presents a new in-the-field self-test approach for a specific VLIW processor model with emphasis on the diagnostic capability of the test. It is intended to be used as start-up test in-the-field in order to localize permanently defect components in a VLIW processor model, which provides self-repair capability. In order to overcome the drawbacks of several existing self-test techniques,...
This paper presents an on-line distributed induction motor monitoring system based-on the ARM (Advanced RISC Machines), which is integrated with the embedded and CAN (Controller Area Network) bus technologies. The hardware structure of the system with the ARM microprocessor S3C2410X and CAN bus controller MCP2510 is introduced, the accomplishment of software of motor on-line monitoring system is also...
This paper introduces an intelligent roots flow meter based on ARM Cortex-M3 processor and μC/OS-II embedded real-time operating system. ARM Cortex-M3 processor is an industry-leading 32-bit processor with lower power consumption and higher performance than other 8-bit or 16-bit processors. Using the μC/OS-II embedded real-time operating system, it will compensate the temperature and pressure of the...
As communication networks move towards 40/100G transmission capacities, wire-speed packet processing is becoming much critical to implement. Most commercial solutions for the high-speed telecom market are based on either ASIC designs and/or network processors (NPs), while enterprise solutions can eventually make use of general purpose processors (GPPs) to deal with much slower processing requirements...
To improve the speed of the image processing chip, to quick share the market and to reduce costs, this paper designs a chip with Harvard Architecture and FPGA. The chip is also used with a new hardware algorithm. Using the chip, the processing time is 13.2% less than the time of the chip with Von Neumann Architecture. The used units of filter are 13% of the whole FPGA gates, less than the claim part...
Neuromorphic systems have been increasing in size and complexity in recent years, thanks also the adoption of the Address-Event Representation (AER) as a standard for transmitting signals among chips, and building multi-chip event-based systems. AER mapper devices that route Address-Events from multiple sources to different multiple destinations are crucial components of these systems, as they allow...
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