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Before a microchip's concrete implementation is available a very abstract model is created, e.g., on Electronic System Level (ESL) or even more abstract. To ensure a better design understanding, we propose an automated mapping from a given abstract model to an unfamiliar concrete implementation at Register Transfer Level (RTL). But how to map a variable from the abstract model to a variable from the...
Information Flow Tracking (IFT) provides a formal methodology for modeling and reasoning about security properties related to integrity, confidentiality, and logical side channel. Recently, IFT has been employed for secure hardware design and verification. However, existing hardware IFT techniques either require designers to rewrite their hardware specifications in a new language or do not scale to...
We present a technique to automatically generate System Verilog-Assertions from designs using dynamic dependency graphs. We extract relations between signals of the design using only a few simulation runs, which drastically reduces the required number of use cases compared to other approaches. Additionally, unlike previous approaches, we do not use expression templates to establish those relations...
This poster will describe a taped-out 2×2mm 1.3 M-transistor test chip in IBM 130 nm designed using our new Python-based hardware modeling framework. The goal of our tapeout was to demonstrate the ability of this framework to enable Agile hardware design flows.
Custom hardware accelerators are widely used to improve the performance of software applications in terms of execution times and to reduce energy consumption. However the realization of an hardware accelerator and its integration in the final system is a difficult and error prone task. For this reason, both Industry and Academy are continuously developing Computer Aided Design (CAD) tools to assist...
Nowadays, the design of applications based on smart systems requires the joint simulation of both digital and analog aspects. Even if analog-mixed-signal (AMS) extensions of hardware description languages are an enabling factor, they do not provide a general methodology for the integration of AMS models into digital virtual platforms. This paper defines the problem and provides two main contributions:...
Efficient estimation of power consumption is vital when designing large digital systems. The technique called power emulation can speed up estimation by implementing power models alongside a design on an FPGA. Current state-of-the-art power emulation methods construct models using various custom techniques, but there is no study on how the existing methods relate to each other nor how their differences...
Since its introduction, SystemC-AMS extensions to SystemC have been used in several applications to model the analog part of a heterogeneous SoC. In this case, the SoC is usually a pure simulation model where the digital part is modeled using SystemC. If an emulation verification environment is used, the digital part of the SoC would be running on the emulator while the analog part, modeled with SystemC-AMS,...
Systems on chip (SoC) nowadays, have become heterogeneous in nature. They can be composed of a mix of analog and digital components. In some verification environments, SystemC models the digital components and SystemC-AMS extensions can be used to model the analog part. In an emulation environment, the digital components would be probably running on the emulator while the SystemC-AMS components would...
Technology trends prompting architects to consider greater heterogeneity and hardware specialization have exposed an increasing need for vertically integrated research methodologies that can effectively assess performance, area, and energy metrics of future architectures. However, constructing such a methodology with existing tools is a significant challenge due to the unique languages, design patterns,...
This paper presents the simulation of reentrant excitation-conduction of cardiac cells realized by coupling 80 active circuits in one dimensional (1D) ring-shaped based on FitzHugh-Nagumo (FHN) model. 1D ring-shaped cable model is designed using Simulink in order to simulate an action potential signal and its conduction for a hardware design by using HDL Coder to automate the model for Very High Speed...
We propose a design approach to integrating correct-by-construction formal modeling with hardware implementations in VHDL. Formal modeling is performed within the Event-B framework that supports the refinement approach, i.e., stepwise unfolding of system properties in a correct-by-construction manner. After an implement able model of a hardware system is derived, we apply an additional refinement...
This paper conceptualizes and comments an Hardware-In-the-Loop-based methodology for the design and test of wireless links based on Impulse-Radio UWB. The paper analyses standard HDL simulation EDA tools for interfacing compatibility with the physical peripherals in a generic HIL configuration to define a general Hardware-In-the-Design methodology, i.e. the HIL validation in the first steps of a standard...
Available simulators for testing Hardware Descriptive Language (HDL) codes provide output with respect to simulator clock. This output is not sufficient for the analysis of Field Programmable Gate Array (FPGA) based embedded controllers. The embedded controllers give actuation signal to the plant and receives plant output as the feedback signal. Therefore a coupling between embedded and plant simulators...
Current high-level synthesis tools based on C/C++ offer only limited support for recursion and functions pointers. We present a novel approach for high-level synthesis that represents the program as a term rewriting system. Based on this concept, dynamic creation of threads, parallel recursive tasks and data-dependent branching can be supported in hardware. Complex examples are used to show the effectiveness...
This paper describes a methodology to transform hardware components given as cycle-accurate, synthesizable HDL code to enable their efficient integration into a Simulink simulation. As long as the event-driven HDL model fulfills a few requirements, it can be converted to a monolithic function which allows its native execution in the time-driven model of computation of Simulink without affecting the...
This paper outlines the application of a Model-Checker to the functional verification of a microprocessor's physical electronic implementation. The goals are (1) testing at hardware speed, (2) reduced labor of test bench creation, and (3) a raised level of abstraction for the specifications. L. Lamport's TLC Model-Checker is used to verify a custom version of the Xilinx PicoBlaze Micro-Controller...
In medical research it is of great importance to be able to quickly obtain answers to inquiries about system response to different stimuli. Modeling the dynamics of biological regulatory networks is a promising approach to achieve this goal, but existing modeling approaches suffer from complexity issues and become inefficient with large networks. In order to improve the efficiency, we propose the...
This paper describes a collaborative effort between Mentor Graphics and Portland State University to introduce hardware emulation into the undergraduate and graduate electrical and computer engineering curriculum. We detail several parallel approaches that address a need for both broad exposure to the concepts of hardware emulation and more in-depth experience with transaction-based verification.
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