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Cyber-Physical Production Systems are characterized by integrating sensors, processing and communication in Industrial Environments like in advanced manufacturing plants or in the new generation Smart Grids. In these context, the accuracy on the synchronization plays a vital role because it is the base for control operations and for the correlation among the distributed sensor data sampling. In this...
Up to now, real-time two dimensional (2D) chemical images are not available in a simple platform, results from big data with low generating rate by complicated process including movement of light source and ultra-low current measurement. A synchronization of all inputs including coordination of scanning step, ac signal of laser spot, and dc bias of LAPS is achieved by a field-programmable gate array...
The Wave Dynamic Differential Logic (WDDL) offers an effective way to resist Side Channel Attacks (SCA). But, it suffers from early propagation and routing imbalance between dual signals. In this paper, we deal first with the EPE problem. We study the security of BCDL logic, which is known to counter early propagation, and we compare it to WDDL logic. We target a custom tree-based FPGA of 2048 cells...
The significant PVT variations seen with modern technologies make synchronous design inefficient. Asynchronous design with its flexible timing is a promising alternative, but prototyping is difficult on the available FPGA platforms which are clock centric and do not provide the required functional primitives like mutual exclusion or Muller C-elements. The solutions proposed in the literature work...
Power dissipation is a bottleneck in the design of low power electronic devices that, operate at high frequencies. Hence, the clock signal is a major source of power dissipation. The technique clock gating at the architecture level can be implemented to reduce the dynamic and clock power. In this paper, the authors aim at implementing, analyzing and comparing the various resource power using clock...
A system implementation framework is presented for configurable high-speed IP over AOS gateway in this paper. Pipeline operation and asynchronous FIFOs are adopted to achieve rate matching and data synchronization between different clock domains. The format of configuration packet of IP over AOS gateway and finite state machine description of protocol are given. The simulation results show that the...
Several solutions for implementing Petri net models on FPGA thanks to a transformation in a VHDL code have been proposed in literature. But none deals with the management of transition conflicts in the specific case of synchronous implementation of interpreted Petri nets. This article presents an automatic method to deal with conflicts from their detection to their implementation on FPGA. One solution...
This paper deals with the complete design of a digital communication receiver on FPGA. Carrier and timing synchronization problems are covered in implementation. Carrier recovery is done using a feedback compensation loop and timing recovery is done using an early late gate. Xilinx ISE is used for simulation and synthesis and the virtex-6 FPGA board is chosen as the hardware platform. Results obtained...
The key problem of the design of frequency meter is to how to rise to measure frequency precision, this paper put forward a high accuracy and wide frequency band frequency meter design based on FPGA and SOPC technical according to each shortcoming of equal precision measurement and absolutely synchronization frequency measurement. Nios ¢ò CPU flexibly chooses measure frequency method according to...
As general international standard, Inter-Range Instrumentation Group (IRIG) time codes were widely used in modern digital world, monitor and measurement system, autocontrol and commercial fields etc. A new design of IRIG-B decode based on Field Programmable Gate Array (FPGA) is proposed in this paper. The results demonstrate that the system runs steadily with high synchronization precision and better...
In this paper, we present BCDL (Balanced Cell-based Dual-rail Logic), a new counter-measure against Side Channel Attacks (SCA) on cryptoprocessors implementing symmetrical algorithms on FPGA. BCDL is a DPL (Dual-rail Precharge Logic), which aims at overcoming most of the usual vulnerabilities of such counter-measures, by using specific synchronization schemes, while maintaining a reasonable complexity...
This paper focus on hardware representation and implementation of graph algorithms in reconfigurable hardware (FPGAs) to speeding up the execution. Generally, software implementations of graph algorithms in high level languages such as C or C++ are lack of speed and efficiency, although they are flexible and cost effective. Moreover, since FPGA is used to implement the algorithms, it can be modify...
In this paper, a novel technique, Input Change Detection (ICD) Circuit is proposed to reduce the dynamic power consumption of the Asynchronous Pipelined Systems with Bundled-Data Protocol. For every operand, a request pulse is given to the asynchronous pipelined system to process the operands, immaterial of whether the successive operands are same or different. This increases the dynamic power consumption...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
The universal serial bus(USB) transceiver macro cell interface (UTMI) is a two wire, bi-directional serial bus interface. The USB2.0 specifications define three types of UTMI implementations depends on data transmission rates, those are low speed (1.5 MHz) only (LS), full speed (12 MHz) only (FS) and high speed (480 MHz)/full speed (12 MHz) (HS). UTMI consists of transmitting and receiving sections,...
This paper presents a bus guardian design used in an in-car network compliant with FlexRay standards. FlexRay is a new standard for data/signal communication among electronic devices installed in a vehicle. An 8051-compatible microcontroller was used to implement the system controller. Most important of all is that the bus guardian (BG) in charge of security and safty is proposed and implemented....
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