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We present thrifty-malloc: a transaction-friendly dynamic memory manager for high-end embedded multicore systems. The manager combines modularity, ease-of-use and hardware transactional memory (HTM) compatibility in a lightweight and memory-effcient design. Thrifty-malloc is easy to deploy and configure for non-expert programmers, yet provides good performance with low memory overhead for highly-parallel...
Multicore embedded systems are rapidly emerging. Hardware designers are packing more and more features into their design. Introducing heterogeneity in these systems, i.e. Adding cores of varying types does provide opportunities to solve problems in different aspects. However, this presents several challenges to embedded system programmers since software is still not mature enough to efficiently exploit...
In this paper, we presents the design of a hardware temporal multi-threading architecture for a Java processor. The Java virtual machine (JVM) model is a stack machine where the process state is the snapshot of the Java stack. If the runtime stack is stored (or cached) in on-chip memory for performance reasons, the backup and restoration of the Java runtime stacks for context switching would be expensive...
The popularity of multicore embedded systems brings new challenges to the development of parallel applications: at the same time it is necessary to exploit the availability of multiple cores, it is also mandatory to consume less energy. To speed up the development process and make it as more transparent as possible to the programmer, parallelism is exploited through the use of Application Programming...
Many embedded systems get improvements on hardware such as massive memory and multi-cores. According these improvements, some application that demands per-formance of excessive operations per seconds has been app-eared. These applications often use dynamic memory allocation. But, existing allocators does not scale well, thus those applications is limited theirs performance by allocators. Moreover,...
The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this paper, we use OpenCL, an industry supported standard for writing programs that execute on multicore platforms and accelerators such as GPUs. Our architectural synthesis tool, SOpenCL (Silicon-OpenCL), adapts OpenCL into a novel...
Currently multicore systems start to be used even in low-end devices such as embedded systems controllers requiring real-time guarantees. Hardware Transactional Memory (TM) is a new synchronization paradigm for this architecture, allowing problems of lock-based methods and making easer programming. We propose to use TM to synchronize the concurrent/parallel execution of the Garbage Collector (GC)...
SystemC is a widely used electronic system-level (ESL) design language that can be used to model both hardware and software at different stages of system design. There has been a lot of research on behavior synthesis of hardware from SystemC, but relatively little work on synthesizing embedded software for SystemC designs. In this letter, we present an approach to automatic software synthesis from...
This paper implements an embedded system current industrial communication protocol. It is based on the fastest EtherCAT, as fast as a PC-based system. The EtherCAT Slave module is easily used due to the Master System composed of the Embedded System.
Real time control applications are very demanding in terms of closed loop system response. The challenge is to execute an operation in a predictable amount of time. As more control functions are needed, faster computing speed is preferred to achieve the desired control responses. The major processor manufacturers have given up trying to make processors run faster, at least for the time being. Instead,...
Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for...
Multi-threaded real-time applications run on platforms that offer services such as concurrency, timing and synchronization. In a model driven context, separation of concerns between functional specification and design choices is one of the key challenges. For that purpose, annotations defined by the MARTE sub-profile for software resource modeling (SRM) provide high level abstractions of target software...
The development of embedded systems requires the development of increasingly complex software and hardware platforms. Full system simulation makes it possible to run the exact binary embedded software including the operating system on a totally simulated hardware platform. Whereas most simulation environments do not support full system simulation, or do not use any hardware modeling techniques, or...
Snoop-based cache coherence protocols are typically used when multiple processor cores share memory through a common bus. It is well known, however, that these coherence protocols introduce an excessive power overhead. To help alleviate this problem, we propose an application-driven customization technique where application knowledge regarding data sharing in producer-consumer relationships is used...
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