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This paper presents a study of the par alle lization possibilities of a Non-Linear Iterative Partial Least Squares algorithm and its adaptation to a Massively Parallel Processor Array manycore architecture, which assembles 256 cores distributed over 16 clusters. The aim of this work is twofold: first, to test the behavior of iterative, complex algorithms in a manycore architecture; and, secondly,...
The scalable extension (SHVC) of the High Efficiency Video Coding (HEVC) allows encoding in layers a video with multiple quality level such as resolution, bit-depth or Signal to Noise Ratio (SNR). Compared to the equivalent HEVC simulcast, the SHVC extension provides inter-layer prediction mechanisms enabling significant bit-rate savings. Moreover these inter-layer prediction mechanisms are less complex...
In this paper, we propose and implement two electronic control unit (ECU) architectures for real-time automotive cyber-physical systems that incorporate security and dependability primitives with low resources and energy overhead. These ECUs architectures follow the multiprocessor system-on-chip (MPSoC) design paradigm wherein the ECUs have multiple heterogeneous processing engines with specific functionalities...
We present the results of a study of the feasibility of implementing real-time track reconstruction within the framework of a pre-existing readout system, using the “Artificial Retina” approach. This is the first attempt at building a complete medium-size prototype of this kind (comprising about 8M Logic Elements, distributed on several separate boards), operating it continuously at its limit speed...
HEVC is the newest standard developed by the Joint Collaborative Team on Video Coding (JCT-VC). HEVC or H.265 includes several modifications compared with its predecessor the H.264/AVC, especially those involved in Fractional Motion Estimation (FME). This work is focused on the FME process that is an important part of an HEVC CODEC, because of its high computational complexity that demands a 40–60%...
Software-Defined Security (SDS), which provides a flexible and centralized security solution by abstracting the security mechanisms from the hardware layer into a software layer, attracts many researchers to study the detail of this conception. One of the key challenges of SDS is how to schedule and orchestrate security appliances according to huge and heterogeneous threat information, especially...
The IBM TrueNorth (TN) Neurosynaptic System, is a chip multi processor [1] with a tightly coupled processor/memory architecture, that results in energy efficient neurocomputing and it is a significant milestone to over 30 years of neuromorphic engineering! It comprises of 4096 cores each core with 65K of local memory (6T SRAM)-synapses- and 256 arithmetic logic units — neurons-that operate on a unary...
In the international standards for architecture descriptions in systems and software engineering (ISO/IEC/IEEE 42010), “concern” is a primary concept that often manifests itself in relation to the quality attributes or “ilities” that a system is expected to exhibit — qualities such as reliability, security and modifiability. One of the main uses of an architecture description is to serve as a basis...
Arduino is an open source platform that offers a clear and simple environment for physical computing. It is now widely used in modern robotics and Internet of Things (IoT) applications, due in part to its low-cost, ease of programming, and rapid prototyping capabilities. Sensors and actuators can easily be connected to the analog and digital I/O pins of an Arduino device, which features an on-board...
Arduino [1] is an open source platform that offers a clear and simple environment for physical computing. It is now widely used in modern robotics and Internet-of-Things (IoT) applications, due in part to its low-cost, ease of programming, and rapid prototyping capabilities. Sensors and actuators can easily be connected to the analog and digital I/O pins of an Arduino device, which features an on-board...
This paper shows how a real-time simulation can be applied for rapid prototyping of an unconventional current regulator in electrical drives. The case study refers to a permanent magnet synchronous motor, with field oriented speed control algorithm arranged in the rotor fixed d-q frame. The novelty introduced in this control scheme is represented by the use of a novel PI current regulator, formerly...
Real-time Ethernet variants are expected to build the future communication infrastructure in cars. First camera based driver assistance functions will communicate using IEEE 802.1 AVBs credit-based shaping. But for the strict timing requirements of automotive control-traffic, AVBs current timing guarantees are insufficient. The upcoming IEEE 802.1Qbv standard proposes synchronous time-triggered traffic...
High Efficiency Video Coding (HEVC) is new video coding standard beyond H.264/AVC. In this paper, an area and throughput efficient 2-D IDCT/IDST VLSI architecture for HEVC standard is presented. Adopting proposed data flow scheduling and shared constant multiplication structure, the architecture supports variable block size IDCT from 4×4 to 32×32 pixels as well as 4×4 pels IDST. Using 65nm technology,...
The standard solution for automotive control networks is the Control Area Network (CAN) bus. Almost any vehicular computer system comprehends at least one CAN line. For the past two decades, software development for control system has been strongly connected to the properties and interfaces of the CAN bus. Currently, the automotive industry is in the middle of a technology leap towards an information-based...
This paper presents a compression analysis about the High Efficiency Video Coding (HEVC) standard targeting a computational effort reduction at the scope of the motion estimation (ME). Restricting the Prediction Units (PUs) — among a total of 24 sizes — to the 4 square-shaped sizes in the HEVC interframes prediction, it is possible to reduce in 74% the number of operations at the cost of 4% increase...
As the performance requirements of today's real-time systems are on the rise, system engineers are increasingly forced to optimize and tune the execution time of real-time software. Apart from usual optimizations targeting the average-case performance of a program, the worst-case execution time bound (WCET) delivered by program analysis tools often has to be improved to meet all the deadlines and...
Architecture Analysis and Design Language (AADL) is a standard that originated in the avionics domain, but is now being used in avionics and other critical distributed real-time embedded system design. AADL provides a formal notation and semantics for capturing an entire distributed platform architecture (hardware components, protocols, and software architecture annotated with properties including...
The new operational environment is exemplified by continuously shifting mission requirements that challenges our Information Systems to dynamically add functionality, increase throughput and overcome threats to deliver new capabilities, quicker, with less cost, and more accuracy. It is essential that we engineer a flexible design and follow an agile development process to keep up with these rapid...
In their early age, E/E (electrical and electronic) systems were OEM (Original Equipment Manufacturers) specific. Adapting existing components to different environments was both time and effort consuming. AUTOSAR (AUTomotive Open System Architecture) is both a consortium founded by the major automotive companies and an architecture standard that allows collaboration on basic E/E functions while providing...
The ARINC-653 standard architecture for flight software specifies an application executive (APEX) which provides an application programming interface and defines a hierarchical framework which provides health management for error detection and recovery. In every partition of the architecture, however, processes may have to deal with asynchronous realtime signals from peripheral devices or may communicate...
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