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Residential gateways play a key role in providing internet access to home consumers. Nowadays, users in the same home with heterogeneous applications share a common gateway. As such, the gateway becomes the bandwidth bottleneck, leading to impairments and negatively affecting users' Quality of Experience (QoE). In the case of delay sensitive applications like video streaming and online gaming, this...
The growing research in reversible computation has been duly complimented by several proposals of reversible circuit synthesis algorithms. A certain amount of proposals have also been presented for optimizing reversible circuit designs. This communication proposes a fresh synthesis algorithm for four bit reversible functions based on a pre-defined library of Control Line Sets. The library contains...
Motivated by the prospects of quantum computation, the design of quantum circuits received significant attention in the recent past. Due to the complex representation of the underlying quantum mechanical phenomena, a two-stage design flow was established in which the desired functionality is first realized in terms of a reversible circuit and, afterwards, mapped into an equivalent quantum circuit...
Recent advances and new trends in high voltage SiC based MOSFETs are analyzed. The main focus is done on design optimization strategies for reducing the on-state resistance. Gate oxide treatments for improving the interface quality resulting in a lower channel resistance are reviewed as well as solutions for lowering the JFET and bulk resistance components. The 3rd quadrant operation, short-circuit...
Closing gate valves at the boundaries of District Metering Areas (DMAs) in Water Distribution Networks (WDNs) allows reducing pressure and leakages through the WDN, as a consequence of changing the hydraulic paths of the system. A two-step strategy was recently proposed for accomplishing such a task. The first step is the optimal segmentation design, based on maximizing the WDN-oriented modularity...
The performance of Carbon Nanotube Field Effect Transistors (CNFETs) depends critically on device parameters such as CNT diameter, number of nanotubes, and inter-nanotube spacing. To achieve a minimum Power-Delay Product (PDP) of the CNFET based digital design, the Genetic Algorithm (GA) is used in this paper to optimize CNFET device parameters. The results of GA optimization are found to be 10 carbon...
The resource constraint is one of the top issues in the Internet of Things network. All activity in the network node should be carefully designed and managed to support the resource efficiency of the network. Hence, an energy efficient transceiver like ZigBee is popularly used as the infrastructure for the Internet of Things edge network. This paper presents our method for efficient ZigBee router...
With fast growth of data centers and automotive electronics, DC-DC converters are the crucial modules, which deliver power to these systems. High conversion ratio (HCR) step down DC-DC converters are gaining growing attention for usage in these high tech emerging applications. The main design challenge of these converters is maximizing conversion ratio, efficiency, and power density simultaneously...
In this paper, a new PNPN tunnel field-effect transistor with L-shaped gate (LG-PNPN TFET) is proposed and investigated by numerical device simulator bringing significant on-state current enhancement. Higher drive current is achieved at VDD = 1.0V than traditional PNPN TFET because of both the line and point tunneling between the source and N+ pocket. Key parameters like the pocket width and doping...
In recent years, dramatic growth of mobile data traffic has left the operators no choice but to consider Wi-Fi networks as an economic complementary solution. To achieve this, WLANs require to adopt some of the key features of carrier-grade operators, such as centralized resource management. As an emerging paradigm, Software Defined Networking (SDN) can be used to provide salient centralized network...
This paper introduces a dead-time optimization technique for a 2-level voltage source converter (VSC) using turn-off transition monitoring. Dead-time in a VSC impacts power quality, reliability, and efficiency. Silicon carbide (SiC) based VSCs are more sensitive to dead-time from increased reverse conduction losses and turn-off time variability with operating conditions and load characteristics. An...
The rapid growth of traffic demands has posed challenges and difficulties on both the radio access networks (RANs) and the backhaul links. To stress these problems, caching technology, more specifically, caching user contents at the infrastructures of different RANs is proposed as an effective approach. In this paper, we consider the joint user association and cache content placement problem in cache-enabled...
This paper mainly presents a design of optimized (15, 4) parallel counter. When testing the design with 15 rows of inputs, synthesis report of our design performs better in respect of delay, area and power consumption than other two existing design. This result shows that processes such as partial product reduction in a multiplier or column-addition in a matrix could be more efficient, especially...
Demonstrated in this work are the effects of lateral scaling on the figure of merit (RDS(on)×QG) for a pGaN, enhancement-mode HEMT. To this end, the drift length (Ldrift) and the length of the gate field plate (LGFP) have been scaled to exhibit the influence of these terms on the on-state resistance (RDS(on)), gate charge (QG), and breakdown voltage (VBR). Results conclude that for a given field plate...
Large scale scientific applications in general and especially cardiac simulations experience different execution phases at runtime and each phase has different computational and communication requirements. An optimal solution or numerical scheme for one execution phase might not be appropriate for the next phase of the application execution. We propose an autonomic management framework, which is built...
Performance slack in IoT applications is routinely exploited in sensor nodes to minimize power by aggressive voltage scaling. However, scaling voltage to sub-threshold levels causes severe degradation in performance and is prone to On Chip Variation (OCV). In contrast, Near Threshold Voltage (NTV) operation offers a good balance between performance loss, OCV and energy reduction and is promising for...
The press-pack IGBT (PPI) modules are characterized by design of double-sided cooling, solderless joint and wire-bondless contact. These features allows them to be utilized in the field where power density and reliability are demanding, especially in multi-MW wind turbine applications. However, owing to the press-pack structure, there is parasitic inductance which can't be neglected in the mechanical...
In this paper we present a self-timed, power proportional, 32-bit ripple-carry adder design using a state-of-the art cell library. The cell library implements a new transistor sizing strategy for subthreshold in a commercial 65 nm low power process. Simulation results show improvements in performance and energy per cycle when compared to a fixed-period design. The adder has applications in the internet...
The Performance, area, and power are most essential factors to be considered and optimize at every step in the design cycle. Design engineers often need to learn about these factors in order make right decisions on design strategies. Power analysis at lower levels of abstraction can provide more accurate analysis than higher levels. Worst case power can be estimated through high activity pattern generation...
This paper proposes a topology optimization method for dual-threshold (DT) independent-gate (IG) FinFET circuits. In the proposed method, a node extraction algorithm is developed to extract the characteristic nodes of a BDD expression, which are suitable to be realized with the compact logic gates based on the DT IG FinFET devices, and then the equivalent replacement program that these extracted characteristic...
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