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ICs are subject to many causes of malfunction such as aging or aggressive environment, while avoiding unwanted behavior of critical applications is a key issue. Monitoring is a cornerstone of safety policies, as it supports triggering counter measures on demand. High Level Synthesis (HLS) allows to easily implement applications in hardware, and some HLS compliant solutions have been reported. These...
Dynamic Partial Reconfigurable Systems can significantly improve the utilization of hardware by performing multiple tasks on the reconfigurable resources in run-time, whereas the limited reconfigurable resources constraint the number of tasks. To achieve efficient operation of systems, it is crucial to increase the utilization of resources while allocating tasks. This paper proposes a novel MER-based...
Today’s datacenters are increasingly becoming diverse with respect to both hardware and software architectures in order to support a myriad of applications. These applications are also heterogeneous in terms of job response times and resource requirements (eg., Number of Cores, GPUs, Network Speed) and they are expressed as task constraints. Constraints are used for ensuring task performance guarantees/Quality...
Network Function Virtualization along with Network Service Chaining envision a reduction in the respective cost that end users, service providers, and network operators are experiencing, while providing complete and high quality services. However, the vast range of available services and the service on-demand model, creates dynamic traffic conditions that necessitates a flexible and automatic network...
MCU resource pool is the key technology of the current video conference systems. By enabling flexible and efficient allocation of MCU ports, it greatly improves the reliability of video conference system, and has been widely used in large-scale enterprises. This paper describes the MCU resource pool scheduling strategy in State Grid Corporation, analyzes the key factors of the system, and proposed...
It is well-known that different applications exhibit varying amounts of ILP. Execution of these applications on the same fixed-width VLIW processor will result (1) in wasted energy due to underutilized resources if the issue-width of the processor is larger than the inherent ILP; or alternatively, (2) in lower performance if the issue-width is smaller than the inherent ILP. Moreover, even within a...
Globalization of the System-on-Chip (SoC) design process poses a serious security alarm for SoC integrators, due to involvement of untrustworthy third party (3P) vendors supplying intellectual property (IP) cores. In this paper, a novel methodology for design space exploration in high level synthesis (HLS) is presented for loop based control data flow graphs (CDFG), which provides secure information...
Multi-core platforms represent the answer of the industry to the increasing demand for computational capabilities. From a real-time perspective, however, the inherent sharing of resources, such as memory subsystem and I/O channels, creates inter-core timing interference among critical tasks and applications deployed on different cores. As a result, modular per-core certification cannot be performed,...
Memory contention among consolidated VMs on the same hardware has created the need for repetitive memorybalancing operations. In an attempt to provide a prompt memory balancing mechanism, we found problems with the retardation of memory reallocation by the reclamation delay. The scheduling of the VMs and their VCPUs generates the delay, the dirtiness of the candidate pages for balancing makes the...
Detecting error or producing correct output is the primary function of a fault secured system. In the context of multi-cycle transient faults, design space exploration (DSE) of an optimal fault secured datapath based on user constraints of area and delay during high level synthesis (HLS) is considered notorious. This is derived from the fact that generation of a user budget bounded multi-cycle transient...
The configuration of a Hadoop cluster is significantly important to its performance, because an improper configuration can greatly deteriorate the job execution performance. Unfortunately, systematic guidelines on how to configure a Hadoop cluster are still missing. In this paper, we undertake an empirical study on key operations and mechanisms of Hadoop job execution, including the task assignment...
We believe that the existing 802.11 MAC layer can be optimized (especially for energy-efficiency) to make Wi-Fi suitable for a wide range of IoT applications. However, there is a lack of low-cost embedded platforms to be used for experimentation with 802.11 MAC. The majority of low-power Wi-Fi modules for embedded systems has closed source firmware and protocol stack implementations, which prevents...
Custom network-on-chip (NoC) structures have improved power and area metrics compared to regular NoC topologies for application-specific systems-on-a-chip (SoCs). The synthesis of an application-specific NoC is a combinatorial problem. This paper presents a novel heuristic for solving the routing path allocation step. Its main advantages are the support of realistic nonlinear cost estimation and the...
'Simulating the Inter-Cloud' (SimIC) is a discrete event simulation toolkit based on the process oriented simulation package of SimJava. The SimIC aims of replicating an inter-cloud facility wherein multiple clouds collaborate with each other for distributing service requests with regards to the desired simulation setup. The package encompasses the fundamental entities of the inter-cloud meta-scheduling...
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