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The GMM classifier for pattern recognition has shown increased intention in many applications such as speaker verification and identification. Such classifier requires a large storage and complex processing units but improved in performances. The performances of the GMM and its hardware complexity are analyzed in this paper. FPGA-based hardware implementation of the Log-Add algorithm is presented...
Recently speaker recognition system became high interesting by researchers for both software and hardware solutions. Different technologies have been adopted to implement speaker recognition system that has performance with optimal time response with acceptable accuracy. Research progresses are going on to provide highly durable and precise recognition system that can be embedded into critical implementation...
Partial reconfiguration on heterogeneous field-programmable gate arrays with millions of gates yields better utilization of its different types of resources by swapping in and out the appropriate modules of one or more applications at any instant of time. Given a schedule of sub-task instances where each instance is specified as a netlist of active modules, reconfiguration overhead can be reduced...
Engineering change orders (ECOs), which are used to apply late-stage specification changes and bug fixes, have become an important part of the field-programmable gate array design flow. ECOs are beneficial since they are applied directly to a placed-and-routed netlist which preserves most of the engineering effort invested previously. Unfortunately, designers often apply ECOs in a manual fashion which...
Recent work in the FPGA acceleration of molecular dynamics simulation has shown that including on-the-fly neighbor list calculation (particle filtering) in the device has the potential for an 80× per core speed-up over the CPU-based reference code and so to make the approach competitive with other computing technologies. In this paper we report on progress and challenges in advancing this work towards...
The following topics are dealt with: high-performance computing; reconfigurable computing; parallel architecture; radio astronomy signal processing; adaptive filtering; and field programmable gate array.
Reconfigurable hardware is now used in high performance computers, introducing the high performance reconfigurable computing. Dynamic hardware allows processors to devolve intensive computations to dedicated hardware circuitry optimized for that purpose. Our aim is to make larger use of hardware capabilities by pooling the hardware and software computations resources in a unified design in order to...
This work presents a low-cost magnetic levitation system that can be very easily built by undergraduate or master degree students, in order to learn several control and electronics topics. The whole design process proposed in the classroom, and the resulting electronics circuits are described. Three different approaches to implement the control system are shown: analog, digital with microcontroller,...
In this paper we examine the idea of implementing communicating sequential processes (CSP) constructs on a Java embedded chip multiprocessor (CMP). The approach is intended to reduce the memory bandwidth pressure on the shared memory, by employing a dedicated network-on-chip (NoC). The presented solution is scalable and also specific for our limited resources and real-time predictability requirements...
The challenges associated with wireless vision sensor networks are low energy consumption, less bandwidth and limited processing capabilities. In order to meet these challenges different approaches are proposed. Research in wireless vision sensor networks has been focused on two different assumptions, first is sending all data to the central base station without local processing, second approach is...
This paper present an efficient technique and mixed-level design of programmable generating accurate reference voltage. The technique comprises a second-order error feedback Σ-Δ modulators sequence, which is then smoothed by a second-order RC filter. An FPGA-based test platform for the 10-bit programmable reference is implemented for hardware realization to verify the proposed design approach. Experimental...
In this paper we propose a hybrid network-on-chip which combines Spatial Division Multiplexing “SDM”-based circuit switching and packet switching in order to efficiently and separately handle streaming and best-effort traffics generated by real-time applications. The SDM technique is used in circuit-switched sub-network in order to increase path diversity, thereby improving throughput and mitigating...
Today's Multi-Processor System-on-Chips incorporate advanced communication mechanisms, called Network-on-Chip, to interconnect multiple resources such as processors, memories and accelerators. The detailed evaluation of these communication networks calls for low-level tools that allow detailed performance analysis at the level of the network instead of the analysis at the Processing Elements. We present...
This paper describes an FPGA-based system capable of computing the distance of objects in a scene to two stereo cameras, and use that information to isolate objects in the foreground. For this purpose, four disparity maps are generated in real time, according to different similarity metrics and sweep directions, and then merged into a single foreground-versus-background bitmap. Our main contribution...
In this paper, we propose a fast barrier synchronization mechanism, targeting Network-on-Chip based many-core architectures. Its salient feature is that, once the barrier condition is reached, the “barrier release” acknowledgement is routed to all processor nodes in a broadcast way in order to save area by avoiding storing source node information and to minimize completion time by eliminating serialization...
In this paper, a 3780-point FFT algorithm combining of Good-Thomas, Cooley-Tukey, and WFTA algorithm is presented and its hardware implementation by using shift rules based on the analysis of the finite word length effect is described. The simulation results show that the output SNR meets the requirement of TDS-OFDM system.
The computing market constantly experiences the introduction of new devices, architectures, and enhancements to existing ones. Due to the number and diversity of processor and accelerator devices available, it is important to be able to objectively compare them based upon their capabilities regarding computation, I/O, power, and memory interfacing. This paper presents an extension to our existing...
Field-programmable gate arrays (FPGAs) can provide an efficient programmable resource for implementing hardware-based spiking neural networks (SNN). In this paper we present a hardware-software design that makes it possible to simulate large-scale (2 million neurons) biologically plausible SNNs on an FPGA-based system. We have chosen three SNN models from the various models available in the literature,...
As researchers push for Exascale computing, one of the emerging challenges is system resilience. Unlike fault-tolerance which corrects errors, recent reports suggest that resilient systems will need to continue to make progress on an application despite faults. A first step in developing a resilient system is to have robust, scalable system monitoring. The work described here presents a novel, minimally-invasive...
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