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This paper proposed a system solution to data transfer and control based on EZ-USB 2.0 for FPGA applications. The data transfer is achieved in Slave FIFO mode of EZ-USB, and the FPGA controlling is realized by PC sending commands to 8051 in EZ-USB FX2 through EP.0 followed by 8051 sending the received commands to FPGA through I2C channel. The proposed solution offers a high-speed data communication...
One I2C protocol design method for reusability was proposed. In this method, design was divided into 3 levels: protocol level, signal level and interface level. Protocol level can be reused without any modification. Signal level can be reused by setting the number of be transferred byte according to specific operation. Interface level can be reused by changing the number of operation mode and the...
Multiprocessor system-on-chip design (MPSoC) is becoming a regular feature of the embedded systems. Shared-bus systems hold many advantages, but they do not scale. Network on chip (NoC) offers a promising solution to the scalability problem by enhancing the topology design. However, standard NoCs are only scalable within a chip. To be able to build infinitely scalable structures, a method to enhance...
Dynamically reconfigurable FPGAs are well known to combine the flexibility of software with the performance of application specific hardware. As such they can be used as powerful but still flexible coprocessors in embedded processor systems. In this paper we analyze different variants for interfacing reconfigurable hardware from an embedded processor. We describe three different on-chip buses and...
Our laboratory has developed a data acquisition system (eMiCES) for small animal positron emission tomography scanners (PET) and other special purpose detector systems for radiotracer imaging applications. For our applications, the electronics had to be able to be mountable inside a rotating gantry. The resulting design consists of a series of modules that can be tailored for individual applications...
For the DAQ in hadron physics experiments at the 3.7 GeV storage ring COSY in FZ Julich a new generation of readout electronics has been implemented. High performance and cost efficiency is achieved by the definition of an optimized parallel backplane bus in the frontend, based on LVDS technology with 80 Mbytes/s nominal throughput. For the readout of the digitizing modules a systemcontroller module...
A reconfigurable PCI interface card (FILAR) with four on-board high-speed serial optical links has been developed for application in DAQ and test systems. FILAR cards, installed in low cost PCs, are currently being used in the combined test-beam of the ATLAS experiment at CERN as well as in several laboratory set-ups. The hardware and firmware design of the module and results from performance measurements...
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