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A 2-D Cellular Neural Network structure with space invariant neural weights is widely used in image processing applications. Recent advances VLSI technology appears to be very promising to use discrete time CNNs for real time vision applications. In this paper, a system-on-chip implementation which consists of a new CNN emulator design and a processor which performs template learning algorithm is...
Packet classification is a core feature needed in firewalls, SDN switches, and QoS routers. Current research to accelerate the classification with hardware employing Field-programmable Gate Arrays (FPGAs) created a variety of approaches, with significant differences in terms of hardware resource requirements, memory usage, configuration update time, and power dissipation. However, there is no optimal,...
An algorithm to reduce computational time for pseudo-dynamic receive beamforming using FPGA is presented. This includes a method to store and retrieve the predetermined delays and other parameters. In addition, we present a simplified implementation method to compute the scanline one sample at a time. The addresses of the echo signal data from different piezoelectric elements are parallel calculated...
In shared memory switch fabrics, cell-copy or address-copy is used to realize multicast or broadcast in the existing queue managers and address-copy will occupy less on-chip memory and so is widely used. When there are a large number of physical ports in the switch, the number of pointer buffers will increase accordingly, which makes it difficult to meet the design requirements in the case where storage...
Traffic classification is used to perform important network management tasks such as flow prioritization and traffic shaping/pricing. Machine learning techniques such as the C4.5 algorithm can be used to perform traffic classification with very high levels of accuracy; however, realizing high-performance online traffic classification engine is still challenging. In this paper, we propose a high-throughput...
Packet classification is a network kernel function that has been widely researched over the past decade. However, most previous work has only focused on achieving high-throughput without considering its energy-efficiency implications. With the rapid growth of Internet, energy-efficiency has become an important metric for networks. We present the design of an energy-efficient packet classifier on Field-Programmable...
Short read mapping is a process to align the short reads, which are fixed-length fragments of the target genome, to a given reference genome to identify the mutations in the target genome. Because of the rapid development of Next Generation Sequencing (NGS) technologies, faster short read mapping is required. In this paper, we propose an FPGA system for the short read mapping based on sort and parallel...
Undoubtedly, Basic Local Alignment Search Tool is one of the most prevalent algorithms in sequence searching and bioinformatics. BLAST is an index-based approach in order to recognize an unknown string of DNA sequence and due to its high computational nature, different types of hardware configurations have been proposed. In this paper, the traditional algorithm is applied; however a new architecture...
The High Efficiency Video Coding (HEVC) standard can achieve significant improvements in coding performance over H.264/AVC. To achieve significant coding improvements in intra-predictive coding, HEVC relies on the use of an extended set of intra-prediction modes and prediction block sizes. This paper presents a unified hardware architecture for implementing all 35 intra-prediction modes that include...
With increasing demands for more flexible services, the routing policies in enterprise network becomes much richer. This has placed a heavy burden to the current router forwarding plane to support the increasing number of policies, primarily due to the limited capacity in TCAM. This hinders the development of new network services. In this paper, we present the design and implementation of a new forwarding...
The rapid development of Next Generation Sequencing (NGS) has enabled to generate more than 100G base pairs per day from one machine. The produced data are randomly fragmented DNA base pair strings, called short reads, and millions of short reads are mapped onto the reference genomes, which are complete genetic sequences, to reconstruct the sequence of the sample DNA. This short read mapping is becoming...
Ternary Content Addressable Memory (TCAM) is widely used in network infrastructure for various search functions. There has been a growing interest in implementing TCAM using reconfigurable hardware such as Field Programmable Gate Array (FPGA). Most of existing FPGA-based TCAM designs are based on brute-force implementations, which result in inefficient on-chip resource usage. As a result, existing...
A CAM-based (Content Addressable Memory) image matching system is implemented on hardware system using FPGA. The system has simple structure, does not employ any Central Processor Units (CPUs) as well as complicated computations. The authors take advantages of CAM which has an ability of parallel multi-match mode for designing the system. Thus increases the matching performance of the system. The...
SRAM-based FPGAs are susceptible to SEUs. To emulate the effects of SEUs, a variety of fault injection techniques have been studied. As FPGA logic density continues to increase, injecting faults into full bit stream is very time consuming. To further study the SEU effects and the mitigation techniques, an advanced precise SEU fault injection technique is studied in this paper. With this technique,...
A flexible dedicated readout system is one of the most important part of any kind of dedicated detection system, especially for its testing phase as well as when the final system is ready for implementation. An obvious choice is to use a FPGA (apart from dedicated front-end electronics) as a first stage of data storage and processing element. Furthermore the FPGA has to prepare and transfer the incoming/processed...
The ISDB-T standard for digital broadcasting incorporates an extensive signal processing scheme in order to achieve reliable data integrity at the remote receiver. Particularly, the time interleaving stage requires a significant memory depth. Common implementations are often based in single-address access memories, which simplifies the algorithm logic but does not provide a cost-effective solution...
This paper describes a micro-architecture for a custom programmable FPGA-based processor, with direct support for streaming and vector computations relying on custom cache memory storage. The processor combines a custom data-path with several parallel data ports for accessing operands in streaming mode thus efficiently supporting nested looping constructs found in high-level languages while mitigating...
This paper presents the design of high performance co-processor used to calculate the posterior probabilities for the embedded speech recognition of CHMM (Continuous Hidden Markov Model) with the MPIE (Maximum Probability Increase Estimation) algorithm to finish the most computation intensive operations in the speech recognition flow. The design of the co-processor is verified on Xilinx FPGA platform...
A digital full calibration processor is proposed to calibrate most known errors in Pipelined ADCs. This approach does not change internal parts of an ADC and compensates errors by digital post-processing of the output bits. The main idea behind the presented technique is to design a processor to find a correction function that gives the relation between the uncalibrated outputs and the calibrated...
In this paper, a multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB) is proposed. The architecture of proposed decoder only utilizes a parallel with 2 for ½ rate and 1 for ¾ rate can meet the throughput requirements for the CMMB standard. Various techniques are employed to significantly reduce memory and logic resources, including a special quantization...
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