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In the paper, a synthesizable combinational integer number divider VHDL model is described that is suitable for implementation in the FPGA devices. The algorithm the divider is based on is briefly introduced. Along the model, testbench for its functional verification is presented. Results of implementation in Xilinx Spartan-3 and Spartan-6 devices — amount of FPGA resources used and maximum delay,...
The paper designs a VGA image and writing display controller with FPGA chip based on EDA technology. The system designs VGA display control module with VHDL, produces the image signal and the control signal with FPGA. In the process of designing the system deposited the color image and the writing information through the LPM module transfer, finally completes video data processing through the simulation...
In this paper, we propose a low-cost sequential and high performance architecture for the implementation of CORDIC algorithm in two computation modes. It suited for serial operation that performs conversion between polar and rectangular coordinate systems, essentially sin/cos, sinh/cosh and arctan computation. In our proposed architecture, radix-2 arithmetic is employed. The design targets real time...
Using fixed-point arithmetic rather than floating-point for data processing can significantly reduce the cost and power consumption of embedded systems. Unfortunately, this also shifts the burden of managing the data representation from run time to compile time, and in many cases the task of compile-time optimization must be done manually. A number of attempts have been made to formalize this process,...
Since the end of 2008, the first FPGAs based on asynchronous logic cells are commercially available. Although the internal logic of the FPGA fabric is based on pure asynchronous logic, the design style for asynchronous FPGAs does not differ from that of classical FPGAs. The design for asynchronous FPGAs can be synthesized in the same way as for synchronous FPAGs from register transfer level based...
A series of experiments has been conducted to show that efficiency improvement in Galois Field (GF) operators does not directly correspond to the system performance at application level. The experiments were motivated by so many research works focusing on performance improvement of GF operators. Numerous variants of operators were formed based on various combination of operation types (multiplication,...
This paper presents a comparative study of field programmable gate array (FPGA) implementation of standard and truncated multipliers using very high speed integrated circuit hardware description language (VHDL). Truncated multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT) etc. Significant reduction...
A new high precision serial multiplier with Most Significant Digit First (MSDF) is presented. This one uses a Borrow-Save (BS) adder to perform the reduction of large length partials products required by the multiplication of large numbers. The results are converted from BS form to the 2's complement representation by the on-the-fly conversion which let the conversion of the digit result as soon as...
The limitation of speed of modern computers in performing the arithmetic operations such as addition, subtraction and multiplication suffer from carry propagation delay. Carry free arithmetic operations can be achieved using a higher radix number system such as Quaternary Signed Digit (QSD). We proposed fast adders based on Quaternary signed digit number system. In QSD, each digit can be represented...
A new high precision serial multiplier with most significant digit first (MSDF) is presented. This one uses a borrow-save (BS) adder to perform the reduction of large length partials products required by the multiplication of large numbers. The results are converted from BS form to the 2's complement representation by the on-the-fly conversion which let the conversion of the digit result as soon as...
It is known that fast, fully combinational leading-digit detector circuits can be generated efficiently by recognizing their inherent hierarchical structure. It is shown herein that this structure is not only hierarchical, but also recursive. This recursivity fully defines a minimal-complexity circuit, thus guaranteeing optimal circuit synthesis. Such a circuit having an N-bit operand generates all...
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