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We propose a column-based split cell-VSS (CS-CVSS) data-aware write-assisted (DAW A) 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOI technology. The proposed write-assist technique (CS-CVSS and DAWA) improve both half-select SNM and write margin. The proposed 3T low leakage read port enhances read sensing margin by minimizing bitline leakage through negative gate to source...
FinFET variability, which is a small amplitude deviation caused by process, cannot be ignored with the scaling of CMOS. This work utilizes the variability as the random source of SRAM Physical Unclonable function (PUF). The impact of the variation has been simulated from device-level to circuit-level. Further research has been done with its influence on SRAM static noise margin (SNM) and SRAM PUF...
The work reports on an innovative design to improve the scalability of misaligned Double Gate (DG) Tunnel Field Effect Transistor (TFET) for operation as dynamic memory. The design optimization is achieved through use of lateral gap on both edges of back gate (G2) that reduces Band-to-Band Tunneling (BTBT) and enhances Retention Time (RT) by a factor of ∼3. The front gate responsible for read mechanism...
Half SRAM cells with strained Si nanowire complementary Tunnel-FETs (CTFET) have been fabricated to explore the capability of TFETs for 6T-SRAM. Static measurements on cells with outward faced n-TFET access transistors have been performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability. The forward p-i-n leakage at certain bias configuration of the...
This work presents a System-on-Chip designed for Energy-Harvested applications. It embeds an ARM® Cortex®-M0+ microcontroller, 4KB RAM, 4KB ROM, an ultra-low power frequency synthesizer, a custom power switch, and a Power Management Unit enabling Active and Sleep modes. The system fabricated in 28 nm FD-SOI technology achieves 2.7pJ/cycle at 16 MHz during active mode, and the core consumes 4.3 nW...
Gate-all-around nanowire transistor is deemed as one of the most promising solutions that enables continued CMOS scaling. Compared with FinFET, it further suppresses short-channel effects by providing superior electrostatic control over the channel. Due to the unique device structure, gate-all-around nanowire transistor also allows more efficient layout design by exploiting 3-dimensional stacking...
The advancing trend to autonomous driving tightens the requirements for automotive microcontrollers with embedded flash memories. High reliability and low latency demands however have prevented the broad usage of multilevel-cell flash in this sector so far. This paper describes a robust time-domain voltage sensing scheme tackling the challenges arising from these tight conditions. A dynamic voltage...
Zynq System-on-Chip (SoC) integrates both Processor and Programmable Logic architectures, where the whole functionality of a system is placed on a single chip. Due to the advancement of process technology, the complexity of circuit analysis becomes harder and the failure modes are becoming marginal, e.g., leakage in nano-ampere range. SoC devices require very challenging work for failure localization...
This paper presents the designs of two digital circuits in which processing of data (stored in volatile and non-volatile memories) is locally performed and routed; these circuits are referred to as data-centric and therefore, amenable to Near-Memory (NM)operation. Two circuits are proposed; they utilize at logic level a 2-2AOI gate, but with different types of selector. Simulation results using HSPICE...
CMOS scaling faces numerous challenges, among which device scaling, interconnect bottleneck, high leakage power and manufacturability are major ones. The scaling challenge is particularly acute for SRAM since maximum performance/power at highest density is required with every new generation. 3-D integration provides possible pathways to overcome the impediments faced in achieving ultra-high density...
Conductive atomic force microscopy (CAFM) was used to investigate nano-electric performances of semiconductor MOS (metal-oxide-semiconductor) devices. Due to the small tip size (as small as ∼20 nm for PtSi probes), CAFM is capable of imaging both topography and current information of nano-device structures simultaneously with very high lateral resolution. Due to the use of wide ranges of current amplifier...
In this paper, a method to detect shorts at the gates of the storage node of a 6T SRAM bit cell via atomic force probing (AFP) at the Via 1 level is discussed. This method is useful for the preservation of physical evidence as well as to ease the probing operation due to the lower density and larger separations of vias compared to contacts. One particular case of single bit failure is documented,...
It is challenging to adopt computing-intensive and parameter-rich Convolutional Neural Networks (CNNs) in mobile devices due to limited hardware resources and low power budgets. To support multiple concurrently running applications, one mobile device needs to perform multiple CNN tests simultaneously in real-time. Previous solutions cannot guarantee a high enough frame rate when serving multiple applications...
In this work, a DRAM cell based on gated-thyristor having pillar channel and sidewall gate is proposed and investigated through device simulation study. Stored electrons in the base region make a difference in read current lowering potential barrier. It has a fast writing speed under 10 ns because of its mechanism based on thermal injection and highly scalable structure because of self-connected word...
We describe a multi-layer security system called "Application Protected Execution" (APEx) that has an "In-VM monitoring" functionality protected by out-of-band memory created within a Virtual Machine (VM) on cloud-based nodes. The In-VM monitor functionality protects execution of security related software and is triggered by hooked system events to avoid context switched overhead...
IoT requirements are almost as varied as the Things to which they are applied, but common demands are maximum battery life with minimum system cost and physical volume. Sub-threshold operation is promising, but even a single un-optimized or always-on component can eliminate low-voltage gains elsewhere. This work presents a highly integrated sub-threshold capable ARM based MCU with fully integrated...
In cyber-physical systems, such as modern industrial plants, complex software is an essential part that enables cost-effective and flexible operation. However, this complexity increases the probability of problems that only reveal themselves after the deployment. This is even more important if security aspects are involved. Therefore, providing the possibility for software updates is an important...
Logical elements for translation lookaside buffers were designed with single-event compensations and simulated on the bulk 65-nm CMOS design rule. The effects of upsets and single-event transients under impacts of single nuclear particles on MOS logical elements were minimized by the hardening the design. The basis of the fault-tolerant design is the hardened main row elements of the common matrix...
In this work, Work-Function Variation (WFV) are studied on 5 nm node gate-all-around (GAA) Vertical Nanoplate FET (NP VFET) in 6-T SRAM using Technology computer-aided design (TCAD) simulation. As WFV effects become intensified, we investigate the WFV effects for an accurate guideline with regard to grain size (GS) and channel area of NP VFET in SRAM bit cells.
In this paper, we will review the current challenges and advancements to continue standard device scaling beyond the 5nm technology node. Apart from the introduction of new materials and device concepts, we will also address the trend towards more heterogeneous systems requiring close interaction between the technology and system optimization.
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