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High-performance computing, enterprise, and datacenter servers are driving demands for higher total memory capacity as well as memory performance. Memory “cubes” with high per-package capacity (from 3D integration) along with high-speed point-to-point interconnects provide a scalable memory system architecture with the potential to deliver both capacity and performance. Multiple such cubes connected...
Static RAM with a traditional topology of DICE designed by scaling with rules less than 65-nm lost advantages in failure tolerance to single nuclear particles compared to CMOS RAM on 6-T memory cells. Transistors of the STG DICE cell have been separated onto two groups so that impact of single nuclear particles on one of the groups do not lead to an upset of the logic state of the cell, but only causes...
This paper discusses multi-point address channel design in fly-by topology for high speed memory interface. Waveform behaviors at DRAM locations along the channel are examined in depth with eye opening data in various channel design factors and device termination settings. Eye opening is exacerbated on the front DRAM from the controller more prominently due to ring-backs from high frequency reflections...
Systems on-Chip (NoC) has created as a promising answer for on-chip interconnection in SoC because of its adaptability, reusability, adaptability and parallelism. It is important to identify and rectify the fault in the Network on Chip. Testing is an important process to find and rectify the fault in Network on Chip. In testing, FIFO buffers produce high throughput gain as well as reduce latency....
High performance embedded applications are developed using system-on-chips (SoCs) which in turn include silicon intensive, integrated application processors. These SoCs integrate multi-core processor (i.e., ARM Cortex9 or A15) with variety of memory interface controllers, communication interface controllers and special purpose accelerators. Traditionally bus matrix is used for integrating these intellectual...
As the amount of digital data the world generates explodes, data centers and HPC systems that process this big data will require high bandwidth and high capacity main memory. Unfortunately, conventional memory technologies either provide high memory capacity (e.g., DDRx memory) or high bandwidth (GDDRx memory), but not both. Memory networks, which provide both high bandwidth and high capacity memory...
Nowadays the applications for real time processing of large amounts of data are encountered increasingly more frequently, as there are lots of system's types that can generate large comprehensive information in a relatively short time. In this paper we focus on sensor-based systems. Such systems may be found in several important domains, such as smart farming, medical field, water management, or smart...
In this paper, an extension of the OVP based MPSoC simulator MPSoCSim is presented. This latter is an extension of the OVP simulator with a SystemC Network-on-Chip (NoC) allowing the modeling and evaluation of NoC based Multiprocessor Systems-on-Chip (MPSoCs). In the proposed version, this extended simulator enables the modeling and evaluation of complex clustered MPSoCs and many-cores. The clusters...
Scalability is a key challenge for digital spiking neural networks (SNN) in hardware. This paper proposes an efficient neuron architecture (ENA) to reduce the silicon area occupied by neurons. As the computation resource (e.g. DSP in FPGAs) is limited for hardware SNNs, the proposed ENA employs a sharing mechanism of computing component at two levels (synapse and neuron) to reduce the occupied resources...
There is a huge number of SDN experimental platforms available such as simulators, emulators and actual testbeds, each of them having different performance metrics. This paper presents a series of performance tests, that can be performed in each of the available platforms, in order to evaluate and rank them in various performance categories. These tests cover performance categories such as experiment...
Multiport CMOS cell with the soft-error immunity based on DICE which is divided into two spaced groups of transistors each of them consisting of four transistors. The larger the distance between these two CMOS transistor groups, a multiport SRAM is more hardened to single event upsets. The result of a single nuclear particle strike only on the one transistor group of a DICE trigger is a single-event...
We show that both the Lempel-Ziv-77 and the Lempel-Ziv-78 factorization of a text of length n on an integer alphabet of size σ can be computed in O(n lg σ) time (linear time if we allow randomization) using O(n lg σ) bits of working space. Given that a compressed representation of the suffix tree is loaded into RAM, we can compute both factorizations in linear time using O(n) space.
This paper presents a design and detailed FFT analysis for CMOS sense amplifiers. Sense amplifiers in association with semiconductor memories are the key elements in defining the overall performance of CMOS memories. The presented design is implemented using C5 process technology using BSIM-4 Spice models. The design includes circuit and operation descriptions, transient signal analysis, FFT analysis,...
Three-dimensional stacked memory is considered to be one of the innovative elements for the next-generation computing system, for it provides high bandwidth and energy efficiency. Particularly, packet routing ability of Hybrid Memory Cubes (HMCs) enables new interconnects for the memories, giving flexibility to its topological design space. Since memory-processor communication is latency-sensitive,...
Three-dimensional stacked memory is considered to be one of the innovative elements for the next-generation computing system, for it provides high bandwidth and energy efficiency. Particularly, packet routing ability of Hybrid Memory Cubes (HMCs) enables new interconnects for the memories, giving flexibility to its topological design space. Since memory-processor communication is latency-sensitive,...
Load balancing is one major cause of the false traceroute link problem in Internet topology measurements. In this paper, the problem of false traceroute links in the presence of per-packet load balancing is illustrated and analyzed. The false traceroute links in the presence of symmetric and asymmetric per-packet load balancing are analyzed and formulized independently. According to our analysis,...
Leakage power dissipation, timing delay and high noise immunity in advanced embedded static random access memories cells are main critical issues in low power battery operated devices. The newly proposed FinFET based highly noise immune Power gated 6T SRAM design is targeting these areas and successfully suppress leakage power dissipation with maintaining stability of data in standby mode. A single...
RPL, the IPv6 Routing Protocol for Low-Power and Lossy Networks, supports both upward and downward traffic. The latter is fundamental for actuation, for queries, and for any bidirectional protocol such as TCP, yet its support is compromised by memory limitation in the nodes. In RPL storing mode, nodes store routing entries for each destination in their sub-graph, limiting the size of the network,...
A lot of video applications such as traffic jam detection and criminal tracking require quick responses for video processing, which rely on a realtime supporting framework. Compared with CPU processors, GPU acceleration can achieve high performance. However in the context of Cloud Computing, GPU-based jobs consume less CPU resources yet occupy a lot more memories compared to CPU-based jobs, especially...
The rapid growth and the distributed sites of the datacenters increase the complexity of control and management processes. A new paradigm which is called Software Defined Systems (SDSys) comes as a solution to reduce the overhead of datacenters management by abstracting all the control functionalities from the hardware devices and setting it inside a software layer. These functionalities are responsible...
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