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Wire bond packaging for semiconductor devices has been the choice of low cost implementation to memory interface and high-speed transceivers. However, accurate characterization for wire bond package remains challenging owing to lack of consistent probing methodology. Meanwhile, semiconductor devices tend to have increasingly higher density of I/O, logic circuits and transceiver circuits yet shrinking...
The Muon Spectrometer of the ATLAS experiment is based on regular arrays of 3 cm diameter high pressure drift tubes (MDT) in a toroidal magnetic field with an associated bending power of about 3 and 5 Tm (barrel and endcap). The gas composition (93%Ar -7%CO2) and gain (2 ??104), chosen in order to limit aging effects, make the drift response function slow and highly non linear. A test beam setup,...
We solve the Maxwell equations to quantify the amount of photo-generation in Si solar cells consisting of arrays of wires instead of bulk thin-films. Published transmission and reflectance measurements suggest that an array of Si wires absorbs sunlight very effectively due to strong diffraction and scattering. However, a detailed theoretical understanding and quantification of the actual photo-generation...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
An important driving force behind the microelectronics industry is the ability to pack ever more features onto a silicon chip, by continually miniaturising the individual components. However, after 2015 there is no known technological route to reduce devices below 10 nm. We demonstrate a complete fabrication strategy towards atomic-scale device fabrication in silicon using phosphorus as a dopant in...
In this study, we fabricated in-plane thermoelectric micro-generators (4 mm times 4 mm) based on bismuth telluride thin films by using flash evaporation method. The thermoelectric properties of as-grown thin films are lower than those of bulk materials. Therefore the as-grown thin films were annealed in hydrogen at atmospheric pressure for 1 hour in a temperature range of 200 degC. to 400degC. By...
A 53 dB gain limiting amplifier for OC-192 and 10 GbE applications is developed in a 50 GHz fT SiGe SOI complimentary bipolar process, and has 5 mV pk-pk sensitivity, 1.25 V pk-pk maximum input signal, 14 ps (20/80%) rise/fall times and 450 mV pk-pk output into matched differential 50 Ohm loads, consuming 430 mW on a 3.3 V supply. Input Cherry-Hooper gain stages limit the -3 dB bandwidth to 11 GHz...
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