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The paper presents design and implementation of a wireless sensor node suitable for medical applications. As physiological signals are highly redundant, the data compression algorithms (Huffman's coding) are used to save energy and improve the node performance. Design is based on the ARM Cortex M1 processor and implemented in FPGA.
This paper describes a self-configurable middleware and a node execution platform to support autonomous sensor networks. We achieve self-configuration by scheduling and strategies similar to load balancing (mapping) that is integrated in our proposed middleware. On the node execution platform we decide on the fly between microprocessor and FPGA realization of hybrid tasks. We propose a combination...
Wireless sensor nodes are essential elements in wireless sensor networks. There are two important issues which need to be considered in order to build a sensor node: low power consumption and scalability. This paper proposes and presents a SoC architecture of wireless sensor node based on open source IP blocks such as OpenRISC 1200 microprocessor core and Wishbone Interconnect Matrix bus core. This...
The introduction of smarter and smaller application specific processors has opened doors to the world of intelligent sensor networks. This has led sensors to have their own onboard processing and communication units. These technological advancements have transcended sensors from performing trivial sensing functions to performing more complex operations like monitoring environmental changes, carry...
Battery-powered sensor nodes call for low power consumption. As a crucial component, a power-efficient sensor network processor greatly reduce the overall power consumption of a node. In the paper, we propose a low-power asynchronous event-driven sensor network processor mapped onto an off-the-shelf clocked FPGA. Since the processor employs a bundled-data asynchronous encoding scheme, we define a...
Wireless sensor networks (WSNs) are typically composed of very small, battery-operated devices (sensor nodes) containing simple microprocessors with few computational resources. However, the rapidly increasing popularity of WSNs has placed increased computational demands upon these systems, due to increasingly complex operating environments and enhanced data-sensing technology. Whereas introducing...
Traditional CPU instructions provide limited support to the byte permutation operation which is frequently used in the various symmetric encryption algorithms. Due to this reason, researcher Ruby B. Lee at Princeton University presented the byte permutation instructions and proved that the byte permutation instructions played an important role on improving the performance of cryptographic algorithms...
We report the design of a digital system to wirelessly control microchip capillary electrophoresis (CE) equipment and a mobile unit for chemical analysis. The digital system consists of an embedded processor designed for digital control, decoding and applying of wirelessly-transmitted test parameters, data acquisition, and mobility control. The design is implemented on a field programmable gate array...
This paper presents a specific processor for sensors networks (PERS), in a first approach, we used the point-to-point topology. We highlight its architecture, its limited instruction set, simulations and performance results when executes the AES and DES algorithm. We have implemented several versions of our PERS in FPGAs, our first version (simple processor) and finalize with our fourth version, which...
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