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In recent CMOS technology, extreme shrinking of contact area at source/drain regions raises serious concerns of high metal/semiconductor contact resistance. Confronting this problem, we introduce a precontact amorphization implantation plus Ti silicidation technique (PCAI + TiSix) and achieve ultralow contact resistivity ($\rho _{c}$ ) of (1.3 – 1.5) $\times 10^{-9} ~\Omega \cdot \text {cm}^{2}$ ...
A novel resistive memory with the TiN/Ti/HfOx/TiN stack is proposed and fully integrated with 0.18 μm CMOS technology. The excellent memory performances such as low operation current (down to 25 μA), low operation voltage (<;1.5 V), high ON/OFF resistance ratio (above 100), and fast switching speed (10 ns) have been demonstrated for this ReRAM. Moreover, the device exhibits excellent scalability...
A new contact RRAM cell realized by TiN/TiON layers stacked between the W-plug and n+ diffusion region inside a small 80 ?? 80 nm contact hole is demonstrated using 90nm CMOS logic technology. This work reports the first time a resistive switching characteristics of the TiON layers sandwiched between the metal and Si substrate. The new Contact ReRAM cell exhibits highly stable read window and very...
High temperature SPM based wet selective processing for multi-step NiPt silicide process on nanoscale CMOS structure with dual gate dense layout has been studied. The high temperature SPM process is found to have better etching selectivity between NiPt/TiN and nickel rich silicide (Ni2Si/Ni3Si2) and results in better sheet resistance (Rs) and uniformity compare to HCL based process. The high temperature...
The long retention, more than 10 years at 85degC, and excellent thermal reliability memory of TiN-CuxO-Cu (with TiN cap layer as top electrode) is reported. TiN cap layer results in more stable reset from low resistance state (LRS) to high resistance state (HRS) under positive pulse and SET under negative pulse, which is beneficial for providing large programming current or voltage on the resistive...
A novel HfO2-based resistive memory with the TiN electrodes is proposed and fully integrated with 0.18 mum CMOS technology. By using a thin Ti layer as the reactive buffer layer into the anodic side of capacitor-like memory cell, excellent memory performances, such as low operation current (down to 25 muA), high on/off resistance ratio (above 1,000), fast switching speed (5 ns), satisfactory switching...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
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