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NAND Flash memory became a standard semiconductor nonvolatile memory. Everyone in the world has widely used NAND Flash memory in many applications, such as digital camera, USB drive, portable music player, smartphone, and tablet-PC. The cloud data server started to use SSD (Solid State Drive) which was based on NAND Flash memory. Recently, 3-dimensional (3D) NAND flash memory was developed and started...
A 7T-SRAM, in which cell data is written by capacitive coupling, is proposed. The elimination of current-drive in read/write operation solves current-conflict problems. No de gradation of noise margin reduces Vddmin by 0.3V∼0.1V. A prototype of 64b 7T-SRAM with 8.74μm2 cell, comparable to 6T-SRAM, using 24nm 3.3V high-voltage CMOS process has been demonstrated for nonvolatile RAMs (NVRAMs) page buffer...
In this paper we propose a new non-volatile charge trap memory architecture implemented on 200mm wafer in 90nm technology node. The aim of this work is to investigate an alternative and scalable solution for embedded low energy applications. The Asymmetrical Tunnel Window (ATW) memory cell has been developed in order to improve the programming operation during a hot carrier injection. The main property...
Cell-to-cell interference in charge trap based TANOS (Tantalum-Alumina-Nitride-Oxide-Silicon) NAND flash memory was investigated. Bit-line (B/L) interference is larger than word-line (W/L) one, which means that the channel coupling by adjacent program string to inhibit string gives larger effect than capacitive coupling to adjacent nitride storage nodes along the string. By separating the total Vth...
As the NAND flash memory market grows rapidly due to various applications, such as USB devices, MP3 players, SSDs, cellular phones, and cameras, there is a requirement for high-density and low-cost devices. Two different approaches to meet these requirements are increasing data per cell and area scaling. 3b/cell or 4b/cell NAND flash memories were introduced as an effective way to lower cost. However,...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
In this work, we have successfully demonstrated SONOS memories with embedded Si-NCs in silicon nitride by in-situ deposition method. The self-assembly silicon nanocrystals were in-situ deposited within the Si3N4 storage layer by dissociation of dichlorosilane (SiH2Cl2) gas to a high density of 9 times 1011 cm-2. This new structure exhibits larger memory windows for up to 6 V, better program/erase...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
The reliability of advanced embedded non-volatile memories has been discussed using the 2T-FNFN devices example. The write/erase endurance and the data retention are the most important reliability parameters. The intrinsic reliability mechanisms can be addressed through single cell evaluation, while the cell-to-cell variation determines the product level reliability. The cell-to-cell variation can...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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