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High performance PZT-on-silicon disk flexure resonators were recently demonstrated with peak |S21| of −1 dB with direct 50 Ω termination, high bandwidth tunability, and high coupling at 22 MHz. This paper explores the performance limits and design optimization of this new resonator in the space of radius and silicon thickness of the (1,1) disk flexure mode. This effort is enabled by the Rapid Analytical/FEA...
Electromagnetic Crosstalk analysis is emerging as a fundamental necessity as a component of electronic system development. With the advent of advanced technologies and System on-Chip (SoC) architectures, ignoring electromagnetic crosstalk is highly risky resulting in significant delays in reaching the market on time as well significant cost over runs. This paper provides an overview of the state of...
A potential technology by silicon interposer enables high bandwidth and low power application processing devices of the future, because the demand of smart mobile products are driving for higher logic-to-memory bandwidth (BW) over 30 GB/s with lower power consumption and ultra-memory capacity. This paper presents a 2.5D-IC structure with silicon interposer to demonstrate electrical performances including...
A potential technology by silicon interposer enables high bandwidth and low power application processing devices of the future, because the demand of smart mobile products are driving for higher logic-to-memory bandwidth (BW) over 30 GB/s with lower power consumption and ultra-memory capacity. This paper presents a 2.5D-IC structure with silicon interposer to demonstrate electrical performances including...
A potential technology by silicon interposer enables high bandwidth and low power application processing devices of the future, because the demand of smart mobile products are driving for higher logic-to-memory bandwidth (BW) over 30 GB/s with lower power consumption and ultra-memory capacity. This paper presents a 2.5D-IC structure with silicon interposer to demonstrate electrical performances including...
Under the platform of a high-speed package system, a modeling method considering all the significant effects from the chip, package, and board levels is developed to identify and investigate the critical nets affecting the signal or power integrity(SI/PI). For SI issues, accurate modelings for signal channel are verified by system of high speed line. The following what-if analyses help to identify...
In this paper, electrical characteristic of TSV (Through Silicon Via) is analyzed. Firstly, equivalent circuit model of TSV is summarized. Modeling and electrical analysis of TSV is conducted, in which TSVs with ideal and non-ideal profiles are compared. And then, multi-TSV configuration in silicon interposer is modeled and analyzed. Capacitive and inductive coupling between TSVs are simulated. With...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
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