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Embedded memory technologies have become a key enabler for systems requiring higher performance, lower power consumption, very small physical volumes, as well as mobility. Specifically, embedded Flash (emFlash) and embedded nonvolatile memories (emNVM) make high performance mobile terminals possible. They also enable the most economic system solutions for devices and applications in the maturing consumer,...
This paper presents the design of high performance co-processor used to calculate the posterior probabilities for the embedded speech recognition of CHMM (Continuous Hidden Markov Model) with the MPIE (Maximum Probability Increase Estimation) algorithm to finish the most computation intensive operations in the speech recognition flow. The design of the co-processor is verified on Xilinx FPGA platform...
A multimedia applications processor is fabricated using a 28nm low-power process technology for ultra-low-power applications. Based on a 4-issue, 32 register version of the TMS320C64X+ VLIW DSP, this System on Chip (SoC) includes 32kB L1 and 128kB L2 caches, and I2S, SPI, UART, MultiMediaCard, and external memory interfaces (Fig. 7.5.1). The design incorporates over 600k instances of custom low-voltage...
The structure of the specialized processor of signal processing in piecewise-polynomial bases was developed and tested. By using MATLAB environment with application standard Simulink we were able to model the algorithms and structure of the specialized processor.
Modern digital signal processors (DSPs) need to support a diverse array of applications ranging from digital filters to video decoding. Many of these applications have drastically different precision and on-chip memory requirements. Moreover, DSPs often employ aggressive dynamic voltage and frequency scaling (DVFS) techniques to minimize power consumption. However, at reduced voltages, process variations...
New generation of telecommunication applications requires highly efficient processing units to tackle with the increasing signal processing algorithmic complexity. They also need to be flexible for handling a large range of radio access technology with specifications moving very fast. As devices including telecommunication features are, per nature, mobile, the high level of flexibility must be achieved...
This paper presents a novel heterogeneous multi-core Digital Signal Processor, named YHFT-QDSP, hosting one RISC CPU core and four VLIW DSP cores. The CPU core is responsible for task scheduling and management, while the DSP cores take charge of speeding up data processing. The YHFT-QDSP provides three kinds of interconnection communication. One is for inner-chip communication between the CPU core...
In order to detect the target position real-timely,a real time target detecting system based on tms320F2812 DSP and Spartan3-SC3S400 FPGA is designed.The design,hardware structure,a target detecting method and software char flow of FPGA and DSP are presented.The system is tested by a 1K×1K image,the processing time is 1.3ms, experiments results show that the method is feasible,the simple design and...
Nowadays embedded processor manufactures extend their architectures to include blocks that perform digital signal processing functions. One of these blocks is address generation units (AGUs) which have been typically provided in digital signal processors (DSPs). The AGUs play an important role in code generation for communication applications where a large number of memory accesses are made. In this...
This paper presents a new algorithm for nighttime contrast enhancement. The proposed algorithm modifies the traditional histogram equalization algorithm to maintain the color information of the original nighttime images. The algorithm has a low computational cost that makes it suitable for real-time hardware implementation. In addition, its efficient hardware implementation is detailed on a Xilinx...
According to architecture characteristics of the motor control digital signal processor (MCDSP), we select standard boundary scan test which is compatible with IEEE 1149.1 as main method, and full scan test as complementary method to test whole chip. Adopted self-definition address registers, data registers, control registers together, boundary scan test makes the use of the original core circuit...
In view of the large and high real-time data transmission in the current strapdown INS, USB interface was integrated into the strapdown INS, and a strapdown inertial navigation real-time data processing system composed of the DSP, FPGA and the USB interface was designed. The system composition and working principle were described; the overall hardware design and software design of the system were...
We propose a new way to save energy in adaptive processors. According to an execution context the custom instruction set of an adaptive processor is selectively 'muted' at run time and thus the energy efficiency is significantly increased. Implemented are multiple so-called 'muting modes' each leading to particular leakage energy savings. A key challenge of this work is to determine which of the muting...
This paper focuses on AVS video encoder implementation and optimization based on TMS320DM6446 DSP. A deep analysis is made of the algorithm of RM52i, which is the reference model of AVS and find the key modules that affect encoding speed. According to the characteristics of the structure, resources and instruction of DM6446, a lot of work have been done at the algorithm level, memory space allocation...
Real-time eye detection is important for many HCI applications, including eye gaze tracking, auto stereoscopic displays, video conferencing, face detection, and recognition. Currently, the eye gaze tracking systems are usually implemented on general purpose processors. As eye gaze tracking algorithms move from research labs to the real world, power consumption and cost become critical issues. This...
A novel technology on extending high speed Memory of DSP is introduced in the paper. There is using IS61LV25616 as a memory of data and using K9F1G08 as a memory of address. The choice of parts of an apparatus, hardware constitution and design of software of the precision signals source based on a high speed memory are recommended in the article.
Following the synthesis and expansion of airborne devices' functions and the requirement of miniaturization of size, the traditional analog IF signal receiving system shows large size, high power consummation and low stability. It is difficult to satisfy the requirement of modern communications. This system applies software radio design thought and implements all digital IF signal processing and 485...
This paper presents a vector control method of AC asynchronous electric motor based on the Digital Signal Processor(DSP) and establishes a mathematical model using double closed-loop decoupled vector control system analysis. The hardware structure, control algorithm and software design flow of the system are described. The key circuit, control circuit and assistant circuit are designed to implement...
In this paper, a color image fusion system based on DSP and FPGA is introduced. In the system, TMS320DM642 is used as the kernel processor to finish the image's fusion arithmetic, storage and display. FPGA, which has the ability to control the logic of image capturing, is used as the assistive processor. The experiment shows that this technology can obtain color fusion image.
Image registration is a stepwise process of overlaying various images of a scene. Accurate image registration in a real time environment has always been a challenge involving the detection of analogous features and then construction of mosaic within plausible accuracy range. Digital Signal Processor is an asset in this regard; its advanced versions equipped with multiple cores can handle many processes...
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