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A 17 GHz current re-use low noise amplifier (LNA) is designed in 0.13 μm CMOS for low power applications such as wireless sensor networks. The LNA also employs transformer based feedback to neutralize the gate-drain capacitance of a MOSFET. The LNA achieves 15.4 dB gain into a 50 Ω load along with 1.9 GHz bandwidth. It features 4.5 dB NF and -12 dBm IIP3 while consuming 7.8 mW of power. A 17 GHz receiver...
A dual-band CMOS low-noise amplifier (LNA) for ISM-band application is reported. For low power and dual band operation, the designed LNA adopts a positive-feedback LC-ladder network. Moreover, for cost effective approach, the LNA has been fabricated using a 0.18-mum mixed-signal CMOS process. The implemented LNA shows gain of 8.3 dB and 11.2 dB, and noise figure (NF) of 6.1 dB and 6.6 dB at 19 GHz...
A 20-GHz 130-nm CMOS front-end using baluns on glass carrier is presented. The front-end consists of a CMOS die featuring a differential two-stage LNA, a passive double balanced mixer, and output buffers, which is flip-chipped on a glass carrier where baluns are realized for the RF and LO signals. The front-end measures a conversion gain of 11 dB, a noise figure of 7 dB, a 60 dB LO to RF isolation,...
This paper presents a concept for integration of ESD protection devices without degrading the high-frequency circuit performance. A differential 18 GHz low-noise amplifier (LNA) has been realized in 0.13 mum CMOS. The ESD protection devices are connected using on-chip inductors. The measured JESDHBM performance is > 2 kV including RF-pins.
A 5.5 GHz LNA implemented in 90 nm RF CMOS process is protected against ESD stress using Above-IC inductors implemented as `Plug and Play', which have very high Q values (40 for 3 nH) compared to BEOL inductors (7 for 3 nH in 5 LM). The RF pin of this LNA withstands an ESD stress above 6 kV HBM and 1 kV MM, the highest ESD robustness value reported ever in a similar circuit. The LNA features a 16...
Design and implementation of ESD protection for a 5.5 GHz Low Noise Amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented. An on-chip inductor, added as ldquoplug-and-playrdquo, is used as ESD protection for the RF pins. The consequences of design and process, as well as the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail and...
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