The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The significant benefit of lock (or wait)-freedom for real-time systems is that by avoiding locks the potentials for deadlock and priority inversion are avoided. The lock-free algorithms often require the use of special atomic processor instructions such as CAS (compare and swap) or LL/SC(load linked/store conditional). However, many machine architectures support either CAS or LL/SC with restricted...
A multi-pipeline dynamically reconfigurable system (MPRS) with coarse-grained processing elements is described in this paper. A systematic mapping method implemented by analyzing a dependence graph with reconfigurable variables (DGRV) based on an MPRS is proposed. The details of the systematic mapping processes are presented and the object functions of the automatic mapping are analyzed. With development...
Previous works in computer architecture have mostly neglected revenue and/or profit, key factors driving any design decision. In this paper, we evaluate architectural techniques to optimize for revenue/profit. The continual trend of technology scaling and sub-wavelength lithography has caused transistor feature sizes to shrink into the nanoscale range. As a result, the effects of process variations...
Scientific Data Management has become essential to the productivity of scientists using ever larger machines and running applications that produce ever more data. There are several specific issues when running on petascale (and beyond) machines. One is the need for massively parallel data output, which in part, depends on the data formats and semantics being used. Here, the inhibition of parallelism...
The performance of parallel programs can be largely affected by the latency of remote memory references. The notion of affinity has been used extensively for scheduling programmer defined threads to reduce remote communication costs. The most popular approach has been to schedule the thread as close to the data as possible. Most of the existing techniques expect the programmer to annotate affinity...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
In array processors, data I/O management is the key to realizing high-speed matrix operations that are often required in signal and image processing. In this paper, we propose an array processor utilizing an effective data I/O mechanism featuring external FIFOs. The FIFOs are used to buffer initial matrix data and partially processed results. Therefore, if all required data are stored in the FIFOs,...
Systolic array is a well known VLSI architecture to achieve extensive parallel and pipelining computing. Many systolic designs have been reported. All are algorithm based, that is one design is only for solving one specific problem. In this paper, the special purpose systolic architecture has been extended into a reconfigurable one and a systematic design approach to mapping two or more algorithms...
Dilated integers form an ordered group of the Cartesian indices into a d-dimensional array represented in the Morton order. Efficient implementations of its operations can be found elsewhere. This paper offers efficient casting (type)conversions to and from an ordinary integer representation. As the Morton order representation for 2D and 3D arrays attracts more users because of its excellent block...
We introduce an architecture for unit tests that traces the values of output variables of JavaScript programming. We present an object model that describes the relationships between tracing and other programming components. We also present six types of tracing statements, implementation and automation approach. We created examples of XHTML and JavaScript programming to illustrate the implementation...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.