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In this paper we propose an implementation technique for sequential circuit using single electron tunneling technology (SET-s) with the example of designing of a “coffee vending machine” with the goal of getting low power and faster operation. We implement the proposed design based on single electron encoded logic (SEEL).The circuit is tested and compared with the existing CMOS...
A minimum in the off current versus gate length characteristics can occur at a threshold voltage maximum for MOS transistors. Sometimes, instead of a minimum, an inflection point can occur at a threshold voltage maximum. We observed that more than one minimum can be experimentally seen. These multiple off current minima can interact with each other and inflection points to create a large range of...
This paper presents a time-area efficient hardware architecture for the multivariate signature scheme Rainbow. As a part of this architecture, a high-performance hardware optimized variant of the well-known Gaussian elimination over GF(2l) and its efficient implementation are presented. The resulting signature generation core of Rainbow requires 63,593 gate equivalents and signs a message in just...
The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit 1GSPS at 1.8 V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further,...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
In this paper, the characteristics of the basic current mirror and the continuous-time current-mode current mirror integrator are analyzed. Using the two unlossy loop integrators and the basic current mirrors, the biquad circuit block is implemented. The signal flow graph (SFG) and the improved leap-frog (ILF) structure are simple to implement the six-order band pass filters. Exploring PSPICE9.1 simulation...
This paper deals with the implementation of a CMOS analog neural network (NN) that has to be integrated in a new kind of optoelectronic measurement system. The aim is to achieve real-time surface recognition using a phase-shift rangefinder and a neural network. NN architecture is a multilayer perceptron (MLP) with two analog input signals provided by the rangefinder, three processing neurons in the...
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