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A new fault modeling and simulation method based on VLSI is proposed to evaluate the fault coverage in VLSI accurately. Firstly, inject the circuit-level faults into the logic gates by means of simulation and experiments. Built the fault dictionary consisted of MTTs by analyzing the experimental effect of faults on function. Secondly, considering the MTTs and their weights, a testing coverage model...
Increase in power density and decrease in supply voltage results in greater power supply current. With scaling, line resistance increases. Together with increase in supply current, this results in ever larger IR drop in supply voltage. IR drop analysis is an important element of power supply network design. Maximizing IR drop is also an important component of manufacturing testing. As a CMOS gate...
Resistive open fault (ROF) represents common manufacturing defects causing extra delays and reliability risks in affected circuits. ROF behavior is sensitive to the supply voltage and the resistance of open (RO). Modeling this fault behavior and detectability with the supply voltage helps in distinguishing between faults as well as testing of multi-voltage designs. While previous ROF models did not...
In this paper, a test is developed for the Operational Transconductor (OTA). The technology used is the 90nm CMOS technology. The assumed fault model consists of six faults per transistor including the open-gate fault. It is proven that only two test values are enough to detect 34 of the possible 36 faults, i.e., a coverage of 94.4%. A Monte Carlo analysis is then performed to study the effect, on...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, even though such defects may affect functional operation. Existing Logic BIST structures suffer from the same limitations. A novel Logic BIST architecture...
Software-based self-test (SBST) has emerged as an effective strategy for non-concurrent on-line testing of processors integrated in embedded system applications. It offers the potential for on-line testing without any hardware overhead. However, test generation is usually based in a semi-automated approach and gate-level information is required for effective test program generation.In this paper we...
This paper describes a methodology for building a reliable internet core router that considers the vulnerability of its electronic components to single event upset (SEU). It begins with a set of meaningful system level metrics that can be related to product reliability requirements. A specification is then defined that can be effectively used during the system architecture, silicon and software design...
Test application at reduced power supply voltage (low-voltage testing) or reduced temperature (low-temperature testing) can improve the defect coverage of a test set, particularly of resistive short defects. Using a probabilistic model of two-line nonfeedback short defects, we quantify the coverage impact of low-voltage and low-temperature testing for different voltages and temperatures. Effects of...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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