The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents a K-band low noise amplifier (LNA) co-designed with ESD protection circuit in 40-nm CMOS technology. By treating ESD devices as a part of the input matching network, an ESD protected 24-GHz LNA is demonstrated with a NF of 3.2 dB under a power consumption of only 4.1 mW. The ESD protection network is composed of dual-diode and a gate-driven power clamp achieving an ESD level of...
This paper presents a low power wideband receiver front-end implemented in 0.18 um CMOS technology for LTE application. The front-end includes a low-noise amplifier and a quadrature passive current commutating mixer. The inductive peaking LNA is designed using common gate topology for wideband matching with low power consumption. A noise cancellation technique is adopted for the LNA to achieve NF...
This article presents a UWB receiver, which is made by the chips designed by our group in SMIC0.18 um process, This receiver was verified by the measurement, With the help of FPGA it can synthesis 2.8G~3.98 GHz LO frequency by changing the PLL and reference frequency, with reference frequency 21 MHz, division ratio 1/160, it can be locked at 3.36 GHz with the phase noise of -83 dBc/Hz, the internal...
This contribution deals with the complete design of a multi-standard GPS/GALILEO front-end, from setting the specifications through to the complete characterization of the device. Special focus will be given to the design for test and the characterization of the design, as optimizing the time spent on this improves time-to-market for the product under development. The highly integrated, low power...
In this paper we propose the superheterodyne receiver beamforming architecture called post-low noise amplifier RF combining (PLRC) to reduce the power consumption by using the single analog-to-digital converter (ADC). The RF chains in our proposed schemes includes the same number of the low noise amplifier (LNA) and the discrete-level phase shifters as the number of antennas followed by the single...
A 60 GHz 4 element bidirectional phased-array TX/RX chip with a 2 bit phase shifter and IF converter to/from 12 GHz, using 90 nm CMOS process, is described. The array features 7 dB gain, measured noise figure (NF) of 9 dB, IP1dB of -19 dbm for RX, and output Psat of +3.5 dBm for TX , drawing 60 mA from a 1.3-V supply. The RMS amplitude and phase error of the phase shifter is 0.7 dB and 2deg max respectively...
This paper presents the design, optimization and methods for test a high frequency high gain low-noise amplifier (LNA), using a UMC RF 0.18 mum CMOS process. The LNA was designed to be part of a low-power/low-voltage RF CMOS transceiver, for operation in the 2.4 GHz ISM band. The LNA has a power consumption of 3.6 mW, for a power supply of only 1.8 V. The LNA has a control signal that makes it to...
Recently, 60 GHz receiver front-ends have emerged, aiming for very high-data-rate communication. From a cost perspective, a highly integrated solution is favorable. Speed and power consumption considerations for the high-data-rate digital part of the chip make 45 nm CMOS a very realistic candidate technology for such systems. This work presents a 150times50 mum2 60 GHz low 1/f noise direct-downconversion...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.