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The usage of Cellular Automata (CA) for image processing tasks in self-organizing systems is a well known method, but it is a challenge to process such CAs in an embedded hardware efficiently. CAs present a helpful base for the design of both robust and fast solutions for embedded image processing hardware. Therefore, we have developed a system on a chip called ParCA which is a programmable architecture...
Digital Signal Processing (DSP) systems involve a wide spectrum of DSP algorithms and their realizations are often accelerated by use of novel VLSI design techniques. Now-a-days various DSP systems are implemented on a variety of programmable signal processors or on application specific VLSI chips. This paper presents the design of Adaptive Finite Impulse Response (FIR) filter for moving target detection...
Now-a-days various Digital Signal Processing systems are implemented on a platform of programmable signal processors or on application specific VLSI chips. Coordinate Rotation Digital Computer (CORDIC) algorithm has turned out to be such kind of programmable signal processor. In recent times, it has been a widely researched topic in the field of vector rotated Digital Signal Processing (DSP) applications...
We connect to the two recent IEEE Signal Processing Magazine special issues on digital signal processing (DSP) on multicore processors (November 2009 and March 2010) and address an issue that was not addressed in the articles there, which we believe has important consequences for DSP algorithm design in the future. The basic observation that we start out with is that in DSP algorithm design, there...
This paper makes a case for developing statistical timing error models of DSP kernels implemented in nanoscale circuit fabrics. Recently, stochastic computation techniques have been proposed where the explicit use of error-statistics in system design has been shown to significantly enhance robustness and energy-efficiency. However, obtaining the error statistics at different process, voltage, and...
New generation of telecommunication applications requires highly efficient processing units to tackle with the increasing signal processing algorithmic complexity. They also need to be flexible for handling a large range of radio access technology with specifications moving very fast. As devices including telecommunication features are, per nature, mobile, the high level of flexibility must be achieved...
The host-multi-SIMD chip multiprocessor (CMP) architecture has been proved to be an efficient architecture for high performance signal processing which explores both task level parallelism by multi-core processing and data level parallelism by SIMD processors. Different from the cache-based memory subsystem in most general purpose processors, this architecture uses on-chip scratchpad memory (SPM)...
Control the data flow between device interfaces, processing blocks and memories in a vision system is complex in hardware implementation. In the research, high-level synthesis tool is used to design, implement and test the vision system within the context of required control, synchronization, and parameterization on a processor based platform. In addition, both HLS tools and HDL were used for the...
This article presents a generator of floating-point exponential operators targeting recent FPGAs with embedded memories and DSP blocks. A single-precision operator consumes just one DSP block, 18 Kbits of dual-port memory, and 392 slices on Virtex-4. For larger precisions, a generic approach based on polynomial approximation is used and proves more resource-efficient than the literature. For instance...
With the advance of semiconductor, multi-core architecture is inevitable in today's embedded system design. Nested loops are usually the most critical part in multimedia and high performance DSP (Digital Signal Processing) systems. Hence, maximizing loop parallelism is an important issue to improve the performance of a modern compiler. This paper studies how to maximize the system performance with...
We describe the reliable vergence eye movement control of a binocular robot vision system based on a disparity computation in the primary visual cortex (V1). The system consists of two silicon retinas, simple cell chips, and an FPGA. The silicon retinas emulate a Laplacian-Gaussian (∇2G)-like receptive field of the vertebrate retina. The simple cell chips generate an orientation-selective receptive...
Decimating band-pass sampled signals have inherent frequency translation property. This frequency translation property has been proposed to be used in software defined radio (SDR) architectures where direct down conversion of single or multiple radio frequency (RF) signals are realized. The digital front-end of such architectures required channel filtering, sample rate conversion, baseband down-conversion...
This paper describes the design of an application specific instruction set processer digital signal processor (ASIP-DSP), for MEMS gyroscope platforms. By profiling the target application, and using the results for optimizing a reference DSP architecture, an optimized DSP architecture can achieve smaller area, and lower power consumption. The reference closed-loop control and signal processing implementation...
The multimedia framework is designed to provide easy to use services for developing multimedia applications based on an embedded platform. With the rapid advances in multimedia technology, various types of codec have been developed. Most of them achieve good performance but construct with complicated algorithms. Moreover, the current computing load of embedded system is still carried by MPU, and its...
In this paper, we propose a Mixed Signal Parallel Multi 1Dimensional Block Matching Algorithm (MSPM-1D-BMA) based motion estimation (ME) processor. In contrast to the typical 2Dimensional full search block matching algorithm (2DFSBMA), the MSPM-1D-BMA based ME processor will greatly reduce the number of data movements in between memories. We employ a voting algorithm in the proposed ME processor to...
This paper presents a new algorithm for nighttime contrast enhancement. The proposed algorithm modifies the traditional histogram equalization algorithm to maintain the color information of the original nighttime images. The algorithm has a low computational cost that makes it suitable for real-time hardware implementation. In addition, its efficient hardware implementation is detailed on a Xilinx...
A High Level Synthesis Framework for mapping DSP algorithms on a Coarse Grain Reconfigurable Architecture is presented. Behavioral specification of the algorithm in C is specified with pragmas in comments and the tool generates configware after performing timing and synchronization synthesis. Pragmas identify SIMD type concurrency and sweep the architectural space with allocation and binding annotations...
This paper describes a System-on-Chip platform architecture for low power high performance Digital Signal Processing intensive applications. The platform is based on the AMBA SoC bus protocol and incorporates a novel interfacing scheme which utilizes the bus hierarchy within AMBA in order to allow single and multiple high performance DSP Intellectual Property cores to be integrated to the SoC platform...
Digital Signal Processing (DSP) system involves a wide spectrum of DSP algorithms for its realization and is often accelerated by use of novel VLSI design techniques. Now-a-days various DSP systems are implemented on a variety of programmable signal processors or on application specific VLSI chips. Coordinate Rotation Digital Computer (CORDIC) algorithm has turned out to be widely researched topic...
New telecommunication systems are based more than ever before on digital signal processing. High speed digital telecommunication systems such as OFDM and DSL need real-time high-speed computation of the Fast Fourier Transform. Thus there is a need of innovative algorithms to improve the speed. In this paper, we propose vedic algorithm for the implementation of multipliers to be used in the FFT. Vedic...
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